SPRAD05B May   2023  – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Board Design
    2. 1.2 Processor Selection
      1. 1.2.1 Note on AM625SIP Data Sheet
      2. 1.2.2 AM625 and AM625SIP Board Design Compatibility
    3. 1.3 Technical Documentation
    4. 1.4 Design Documentation
  5. 2 Block Diagram
    1. 2.1 Constructing the Block Diagram
    2. 2.2 Selecting the Boot Mode
    3. 2.3 Confirming Pinmux (Multiplexing Compatibility)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power
      2. 3.1.2 Discrete Power
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 DDR PHY and SDRAM Power Supply
        1. 3.2.3.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
        2. 3.2.3.2 AM625SIP
      4. 3.2.4 Internal LDOs for IO Groups (Processor IO Groups)
      5. 3.2.5 Dual-Voltage IOs (Processor IOs)
      6. 3.2.6 Dual-Voltage Dynamic Switching IOs
      7. 3.2.7 VPP (eFuse ROM programming supply)
    3. 3.3 Determining Board Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
      2. 3.5.2 AM625SIP
      3. 3.5.3 Note on PDN target impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  7. 4 Clocking
    1. 4.1 Processor Clock Inputs
      1. 4.1.1 Unused WKUP_LFOSC0
      2. 4.1.2 LVCMOS Digital Clock Source
      3. 4.1.3 Crystal Selection
    2. 4.2 Clock Outputs
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 AM625 / AM623
        2. 5.1.1.2 AM625-Q1 / AM620-Q1
        3. 5.1.1.3 AM625SIP
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection of JTAG Interface Signals
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Boot Mode Configuration
    3. 6.3 Resetting the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor Peripherals
    1. 7.1  Selecting Peripherals Across Domains
    2. 7.2  Memory (DDRSS)
      1. 7.2.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
        1. 7.2.1.1 Processor DDR Subsystem and Device Register Configuration
        2. 7.2.1.2 Calibration Resistor Connection
      2. 7.2.2 AM625SIP
        1. 7.2.2.1 Reassigned DDRSS0 Pins on the AMK Package
        2. 7.2.2.2 Calibration Resistors Connection
    3. 7.3  Media and Data Storage Interfaces
    4. 7.4  Ethernet Interface Using Common Platform Ethernet Switch 3-port Gigabit (CPSW3G)
    5. 7.5  Programmable Real-Time Unit Subsystem (PRUSS)
    6. 7.6  Universal Serial Bus (USB) Subsystem
    7. 7.7  General Connectivity Peripherals
    8. 7.8  Display Subsystem (DSS)
      1. 7.8.1 AM625 / AM623 / AM625SIP / AM625-Q1
      2. 7.8.2 AM620-Q1
    9. 7.9  Camera Subsystem (CSI)
    10. 7.10 Connection of Processor Power Pins, Unused Peripherals and IOs
      1. 7.10.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
      2. 7.10.2 AM625SIP
      3. 7.10.3 External Interrupt (EXTINTn)
      4. 7.10.4 Reserved Pins (Signals)
  11. 8 Interfacing of Processor IOs ( LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
    1. 8.1 AM625 / AM623
    2. 8.2 AM625-Q1 / AM620-Q1
    3. 8.3 AM625SIP
  12. 9 Power Consumption and Thermal Analysis
    1. 9.1 Power Consumption
    2. 9.2 Maximum Current for Different Supply Rails
    3. 9.3 Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 AM625 / AM623
      2. 9.4.2 AM625-Q1 / AM620-Q1
      3. 9.4.3 AM625SIP
  13. 10Schematic Design, Capture and Review
    1. 10.1 Selection of Components and Values
    2. 10.2 Schematic Design and Capture
    3. 10.3 Schematics Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Design and Layout Guidelines
      1. 11.2.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
      2. 11.2.2 AM625SIP
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Board Layer Count and Stack-up
      1. 11.4.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
      2. 11.4.2 AM625SIP
      3. 11.4.3 Simulation Recommendations
    5. 11.5 Reference for the Steps to be Followed for Running Simulation
  15. 12Device Handling and Assembly
    1. 12.1 Soldering Recommendations
      1. 12.1.1 Additional References
  16. 13References
    1. 13.1 AM625SIP
    2. 13.2 AM625 / AM623
    3. 13.3 AM625-Q1 / AM620-Q1
    4. 13.4 AM625 / AM623 / AM625-Q1 / AM620-Q1
    5. 13.5 Common for all AM62x family of processors
  17. 14Terminology
  18. 15Revision History

1 Introduction

The Hardware Design Guide for AM625, AM623, AM625SIP, AM625-Q1 and AM620-Q1 family of processors provides a starting point for the board designers designing with any processor of the family of processors. This hardware design guide provides an overview of the recommended design flow and design stages, and highlights important design aspects and requirements that must be addressed. Note that this document does not include all of the information required to complete the board design. In many cases, this document refers to the device-specific collaterals and various other user guide as sources for specific information.

This hardware design guide (document) is organized in a sequential manner. It starts from decisions that must be made during the initial planning stages of the board design, through the selection of key devices, electrical, and thermal requirements. For ensuring a successful board design, issues discussed in each of the section should be resolved before moving to the next section.

Note:

The hardware design guide is applicable to ALW, AMC and AMK package processors.

The hardware design guide may not cover every aspect of the board design.

Note:

These processor families have capabilities to address safety requirements.

The focus of the hardware design guide is non-safety applications.