SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The processor supports one Camera Serial interface (CSI-RX) - 4 Lane with DPHY-RX. Support for 1,2,3 or 4 data lane mode. Refer Multimedia, Camera Serial interface (CSI-Rx) - 4 Lane with DPHY section in the Features chapter of device-specific data sheet for supported data rate. Provided data rate information is for per lane, this will be updated in the next revision of the device-specific data sheet.
The DPHY-RX supports a single clock lane and all the data lanes are clocked at the same frequency. The frame rate is determined by start-of-frame, end-of-frame signaling and allows handling the input sources with different frame rates per channel.
Refer Pin Connectivity Requirements section of the device-specific data sheet for connecting interface pins and supply pins when CSI interface is not used.
For more details, refer the Camera Subsystem section in the Peripherals chapter of the device-specific TRM.