SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The processor supports up to two USB 2.0 Ports. These Ports can be configured as host or device or Dual-Role Device (DRD). USBn_ID (identification) functionality is supported using any of the processor GPIO.
Follow the USB VBUS Design Guidelines section of the device-specific data sheet to scale the USB VBUS voltage (supply connected to the USB interface connector).
VBUS (VBUS supply input including Voltage Divider / Clamp) input is recommended to be connected when the device is configured in device mode. Connection of VBUS (VBUS supply input including Voltage Divider / Clamp) is optional in host mode.
A power switch with OC (over current) output indication is recommended when the USB interface is configured as host. The USB DRVVBUS drives the power switch. It is recommended to connect the OC output to a processor GPIO, when the USB interface is configured as host.
For details related to USB connections and On-The-Go feature support, see the device-specific TRM.
For more details, see the High-speed Serial Interfaces section in the Peripherals chapter of the device-specific TRM.
For connecting the USB pins when USB0 and USB1 are not used or USB0 or USB1 is not used, see the Pin Connectivity Requirements section of the device-specific data sheet.
For more information on USB2.0 interface, see the [FAQ] AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 Custom board hardware design – USB2.0 interface.