SPRADF4 December   2023 TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Basic CLB Implementation
  6. 3Turn-On Delay Configurations
  7. 4Turn-Off Delay Configurations
  8. 5Different Options to Turn On or Turn Off SR PWM
    1. 5.1 Software Control Method
    2. 5.2 Hardware-Based Scheme
  9. 6How to Adjust the SR PWM Clamping Time
  10. 7Summary
  11. 8References

6 How to Adjust the SR PWM Clamping Time

Some applications adjust the max on time for the SR PWM during resonant mode to improve efficiency or compensate for component variations of the resonant tank, as discussed in Implement Three-Phase Interleaved LLC on C2000™ Type-4 PWM. Indicating the match 1 REF value of both Counter 0 and Counter 1 requires adjusting during run time. This adjustment is done with the high-level controller (HLC). The HLC provides communication and data exchange between the CPU and CLB. The CPU can write to a general purpose HLC register R0, to further move the R0 value to the match 1 REF value of counters.

The match 1 REF value does not inherently provide the shadow load mode option, unlike most EPWM registers. However, achieving a similar shadow mode with HLC is possible. Figure 2-3 showcases the zero event of Counter 0 as the Event 0 for HLC since HLC is an event-based system that aligns with the rising edge of EPWM1A. The update of the match 1 REF value for the counters and the EPWM1 module takes effect simultaneously.

Note: To avoid unpredictable behaviors by copying the R0 contents to another CLB register when R0 is being written, add another CLB input with GPREG bit (IN4 in Figure 2-3), and use the lookup tables to take the AND logic of GPREG bit and the zero event of Counter 0 as the HLC trigger event.

The following example codes can be used to update and adjust the SR PWM clamping time.

//before update R0 register, set in4=0 
 CLB_setGPREG(CLB_SR_BASE, 0x00);
 //update the clamp duty cycle for EPWM2A and EPWM2B
 CLB_writeInterface(CLB_SR_BASE, CLB_ADDR_HLC_R0, clamp_duty);
 //set input4 to 1 allow copy of R0 to counter match1 register
 CLB_setGPREG(CLB_SR_BASE, 0x10);