SPRADK1 September 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1
Due to the periodicity and square-shaped attributes of the digital clock signal, most of the energy of the clock concentrates at the center frequency and odd harmonics. SSC modulates the clock nominal frequency in a controlled manner to reduce the radiated emissions of the clock signal itself. In the frequency domain, SSC reduces the peak amplitude of the digital clock signal by spreading the localized peak energy across a wider frequency range. In the time domain, SSC injects jitter to the clock signal, but the voltage amplitude remains unchanged. The SSC of the SoC is fully described using the following parameters: modulation rate, modulation depth, spread type, and modulation profile.
Figure 1-1 shows the SSC characteristics using a common triangular-shape SSC modulation profile. SSC can be configured for the clock signal to either produce a symmetrical modulated output or configured to produce a down spread modulated output. The down spread type reduces the clock frequency from the center frequency.