SPRADK4 October   2024 AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2OptiFlash Technology
  6. 3OptiFlash Hardware Accelerators
    1. 3.1 RL2_OF Accelerators
      1. 3.1.1 RL2-Flash Cache
      2. 3.1.2 FLC - Fast Local Copy (Image Download Acceleration)
      3. 3.1.3 Region-Based Address Translation (RAT)
    2. 3.2 FSS Accelerators
      1. 3.2.1 On-the-fly-Safety Engine
      2. 3.2.2 On-the-fly-Security Engine
      3. 3.2.3 FOTA HW Engine
  7. 4OptiFlash SW Tooling
    1. 4.1 Smart Placement
    2. 4.2 Smart Layout
    3. 4.3 Optishare
    4. 4.4 Dynamic Overlay
  8. 5Benchmarks and Performance Data
  9. 6Usecases for OptiFlash Accelerators
  10. 7Getting Started With OptiFlash
  11. 8Conclusion

Abstract

Emerging applications in the Microcontroller world have led to an increase in memory and performance requirements. For instance, application software in automotive industry like networking, zonal, and so forth that runs on high-performance microcontrollers demand for more memory size for storing firmware, stacks and libraries, and more processing power- multi-core CPUs running at frequencies of 200MHz to 1GHz. Firmware updates further add up to the memory requirement, for downloading the new application image, in addition to what is available for running the existing image.

OptiFlash technology, which is TI’s differentiated memory technology, enables high performance and low-cost solution by right mix of on-chip SRAM and external flash. AM26x family of SoCs with integrated OptiFlash technology as discussed in this paper aims to solve the limitations faced by traditional high-performance MCUs with external flash, by providing hybrid execution from internal SRAM and directly from external flash (also knowns as, execute in place (XIP)), with a goal of reaching XIP performance from external flash to that of internal SRAM.

The major cost advantage of this solution is that the internal SRAM can now be sized lower than the application image size, and the silicon die-cost without embedded flash/NVM is much cheaper due to reduced number of masks and cheaper equipment. This solution also provides scalability in terms of the size (in the order of MBytes) and parts on Board based on Customer need.