SPRADN0 December   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Programming Fundamentals
  5. 2Introduction
    1. 2.1 Hardware Security Module
    2. 2.2 ROM Bootloader
    3. 2.3 Combined Image with X.509 Certificate
  6. 3Flash Kernel Implementation
    1. 3.1 CPU1 Firmware Upgrade (HS-FS)
    2. 3.2 Key Provision (HS-FS to HS-KP)
    3. 3.3 CPU1 Secure Firmware Upgrade (HS-KP/SE to HS-SE)
    4. 3.4 HSM Firmware Upgrade (HS-KP/SE to HS-SE)
    5. 3.5 SECCFG Code Provisioning (HS-KP/SE to HS-SE)
  7. 4Host Application: UART Flash Programmer
    1. 4.1 Overview
    2. 4.2 Build UART Flash Programmer with Visual Studio
    3. 4.3 Build UART Flash Programmer with CMake
    4. 4.4 Packet Format
    5. 4.5 Kernel Commands
  8. 5Example Usage
    1. 5.1 Loading the Flash Kernel onto the Device
      1. 5.1.1 Hardware Setup
      2. 5.1.2 Running the UART Flash Programmer
    2. 5.2 CPU1 Device Firmware Upgrade (HS-FS only)
    3. 5.3 Convert HS-FS to HS-SE
    4. 5.4 Loading a RAM-based HSMRt Image
    5. 5.5 Key Provision (HS-FS to HS-KP)
    6. 5.6 Code Provision (HS-KP/SE to HS-SE)
  9. 6Troubleshooting
    1. 6.1 General
    2. 6.2 UART Boot
    3. 6.3 Application Load
  10. 7Summary
  11. 8References

ROM Bootloader

The basic idea of a flash kernel and how the firmware upgrades has been described, the next section details the first step of the process: loading the kernel to RAM via bootROM.

At the beginning, the device boots and, based on the boot mode, decides if the device executes the code already programmed into the Flash memory or load in code using one of the ROM loaders. This application note focuses on the boot execution path when the emulator is not connected.

Note: This section is based on the F29H85x device. Specific information for a particular device can be found in the ROM Code and Peripheral Booting section of the device-specific technical reference manual (TRM).
Table 2-2 Default Boot Modes for F29H85x devices
Boot Mode GPIO72 (default boot mode select pin 1) GPIO84 (default boot mode select pin 0)
Parallel I/O 0 0
UART 0 1
CAN 1 0
Flash 1 1

After the boot ROM readies the device for use, the device decides where to start executing. In the case of a standalone boot, the device does this by examining the state of two GPIOs (as seen in Table 2-2 , the default choices are GPIO 72 and 84). In some cases, two values programmed into one time programmable (OTP) memory can be examined. In the implementation described in this application note, the UART loader is used, so at powerup GPIO 84 must be forced high and GPIO 72 must be forced low. If this is the case when the device boots, then the UART loader in ROM begins executing and operates at a baud rate of 115200. At this point, the device is ready to receive code from the host.

A major difference between the previous C28-based devices and the F29H85x is the inclusion of the Hardware Security Module (HSM). All boot flows require the HSM to authenticate the incoming image before the boot flows can be executed.

Please see the ROM code and Peripheral Booting section of the Technical Reference Manual (TRM) for details on the boot flow. And Device Boot Flow Diagrams section, on how the HSM and C29 CPUs communicate during the boot sequence.