SPRUIW3 October   2021 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Trademarks
  2. 1Feature Differences Between F28004x and F28003x
    1. 1.1 F28004x and F28003x Feature Comparison
  3. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ Package
      1. 2.1.1 100-Pin PZ Migration for Existing PCB
      2. 2.1.2 100-Pin PZ Migration for New PCB Design
    2. 2.2 PCB Hardware Changes for the 64-Pin PM Package
      1. 2.2.1 64-Pin PM Migration for New and Existing PCB
  4. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28003x
      1. 3.1.1  TMU Type1
      2. 3.1.2  Fast Integer Division (FINTDIV)
      3. 3.1.3  Host Interface Controller (HIC)
      4. 3.1.4  Background CRC (BGCRC)
      5. 3.1.5  Standby Low Power Mode
      6. 3.1.6  X1 GPIO Functionality
      7. 3.1.7  Diagnostic Features (PBIST/HWBIST)
      8. 3.1.8  Advance Encryption Standard (AES)
      9. 3.1.9  Secure Boot/JTAG Lock
      10. 3.1.10 Modular Controller Area Network (MCAN)
      11. 3.1.11 Embedded Pattern Generator (EPG)
      12. 3.1.12 Live Firmware Update (LFU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 XTAL Module
      2. 3.5.2 PLL
      3. 3.5.3 PIE Channel Mapping
      4. 3.5.4 Bootrom
      5. 3.5.5 CLB and Motor Control Libraries
      6. 3.5.6 ERAD
      7. 3.5.7 GPIO
      8. 3.5.8 AGPIO
      9. 3.5.9 ERROR Status
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 DCDC
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  5. 4Application Code Migration From F28004x to F28003x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 Minimum Compiler Version Requirement for TMU Type 1
    4. 4.4 C2000Ware Examples
  6. 5Specific Use Cases Related to F28003x New Features
    1. 5.1 HIC
    2. 5.2 FINTDIV
    3. 5.3 TMU Type1
    4. 5.4 AES
    5. 5.5 MCAN
    6. 5.6 EPG
  7. 6EABI Support
    1. 6.1 Flash API
    2. 6.2 NoINIT Struct Fix (Linker Command)
    3. 6.3 Pre-Compiled Libraries
  8. 7References

1.1 F28004x and F28003x Feature Comparison

An overlaid block diagram of F28004x and F28003x is shown in Figure 1-1 while feature comparison of the superset part numbers for the F28003x and F28004x devices is shown in Table 1-1.

GUID-20201014-CA0I-6XSW-ZSQM-JZMDWK3BX0QW-low.gif Figure 1-1 F28003x and F28004x Overlaid Functional Block Diagram

Table 1-1 F28004x and F28003x Superset Device Comparison
Feature F28004x F28003x
100-Pin PZ 64-Pin PM 56-Pin RSH 100-Pin PZ 80-Pin PN 64-Pin PM 48-Pin PT
Processor and Accelerators
C28x Frequency (MHz) 100 120
FPU Yes Yes (instructions for Fast Integer Division)
VCU–I Yes –
VCRC – Yes
TMU Yes – Type 0 Yes – Type 1 (instructions supporting NLPID)
CLA – Type 2 Available Yes
Frequency (MHz) 100 120
6–Channel DMA – Type 0 Yes
External interrupts 5
Memory
Flash 256KB (128Kw) 384KB (192Kw)
RAM Dedicated 4KB (2Kw)
Local Shared 32KB (16Kw)
Message 0.5KB (0.25Kw) 1KB (0.5Kw)
Global Shared 64KB (32Kw) 32KB (16Kw)
Total 100.5KB (50.25Kw) 69KB (34.5Kw)
Message RAM Types 512B (256w) CPU–CLA 512B (256w) CPU–CLA 512B (256w) CLA–DMA
ECC FLASH, Mx FLASH, Mx, LSx, GSx, Message RAM
Parity LSx, GSx, Message RAM, CAN RAM ROM, CAN RAM
Code security for on–chip flash and RAM Yes
System
Configurable Logic Block (CLB) 4 Tiles – Type 2 4 Tiles – Type 3
Embedded Pattern Generator (EPG) - Yes
Motor Control Libraries in ROM Yes
32–bit CPU timers 3
Advance Encryption Standard (AES) – Yes
Background CRC (BGCRC) – Yes
Live Firmware Update (LFU) Support Yes Yes, with enhancements and flash bank erase time improvements
Secure Boot – Yes
JTAG Lock – Yes
HWBIST – Yes
Nonmaskable Interrupt Watchdog (NMIWD) timers 1
Watchdog timers 1
Crystal oscillator/External clock input 1
Internal oscillator 2
Pins and Power Supply
Internal 3.3v to 1.2v Voltage Regulator VREG LDO Yes
DCDC Yes –
GPIO pins 35 21 20 51 39 26 14
Additional GPIO 5 (2 from cJTAG, 1 from X2 and 2 from DCDC) 4 (2 from cJTAG and 2 from X1/X2)
AIO (analog with digital inputs) 21 14 12 23 16 16 14
AGPIO (analog with digital inputs and outputs) - 2 2 - -
Analog Peripherals
ADC 12–bit Number of ADCs 3
MSPS 3.45 4
Conversion Time (ns) 290 250
ADC channels (single–ended) - includes the two gpdac outputs 21 14 12 23 18 16 14
Temperature sensor 1
Buffered DAC 2
CMPSS (each CMPSS has two comparators and two internal DACs) 7 6 5 4
PGA (Gain Settings: 3, 6, 12, 24) 7 5 4 –
Control Peripherals
eCAP/HRCAP modules 7 (2 with HRCAP capability) – Type 1 3 (1 with HRCAP capability) – Type 2
ePWM/HRPWM channels – Type 4 16 (16 with HRPWM) 16 (8 with HRPWM)
eQEP modules 2 – Type 1 1 – Type 1 2 – Type 2
SDFM channels 4 – Type 1 3 – Type 1 8 – Type 2
Communication Peripherals
CAN (DCAN) – Type 0 2 1
CANFD (MCAN) – Type 2 – 1
FSI 1 (1 RX and 1 TX) – Type 0 1 (1 RX and 1 TX) – Type 2
I2C – Type 1 1 2
LIN – Type 1 1 2
HIC - Type 1 No Yes
PMBus – Type 0 1
SCI – Type 0 2
SPI – Type 2 2
Package Options, Temperature, and Qualification
Junction temperature (TJ) –40°C to 125°C –40°C to 150°C
Free-Air temperature (TA) –40°C to 125°C
Package Options with AEC-Q100 Qualification available Yes Yes – Yes – Yes Yes