SPRUJ09D March   2022  – September 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Control Card Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 HSEC 180-pin Control Card Docking Station
    5. 3.5 Compliance
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
      4. 4.1.4 Power Sequence
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
    4. 4.4 JTAG Path Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 RGMII
      2. 5.6.2 PRU-ICSS
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 HSEC Pinout and Pinmux Mapping
  8. 5References
    1. 6.1 References
    2. 6.2 Other TI Components Used in This Design
  9.   Revision History
  10.   A E2 Design Changes
  11.   B E1 HSEC Pinout Table

4.17 ADC and DAC

The AM263x Control Card supports 24 ADC signal channels that are mapped for the AM263x SoC and terminated to the HSEC connector. All ADC signals are ESD protected (TPD4E001DBVR).

GUID-20220426-SS0I-0TFR-JJKC-L4T5ZQN8XBLM-low.png Figure 4-26 ADC HSEC Connections

There are two muxes (TMUX1136DQAR) that determine the pathing of ADC signals to and from the HSEC Connector.

Table 4-18 ADC MUX Select Logic
MUX Select Signal Condition Function Description
ADC1_MUX_SEL SEL Signal HIGH S1A → D1 HSEC_ADC0_AIN0 selected
S2A → D2 HSEC_ADC0_AIN1 selected
SEL Signal LOW S1B → D1 HSEC_DAC_OUT selected
S2B → D2 HSEC_DAC_OUT selected
ADC2_MUX_SEL SEL Signal HIGH S1A → D1 HSEC_ADC4_AIN0 selected
S2A → D2 HSEC_ADC4_AIN1 selected
SEL Signal LOW S1B → D1 ADC_CAL0 selected
S2B → D2 ADC_CAL1 selected

There are three switches that are used to configure the reference voltages for the ADC and DAC.

GUID-20220426-SS0I-MSDW-C6ND-ZM1LMJQSKW7N-low.png Figure 4-27 ADC Switch Routing
  • The VREF Switch (SW8) is a single pole double throw switch that controls which 1.8 V reference will be used for ADC and DAC.
    Table 4-19 VREF Switch
    VREF Switch Position Reference Selection
    Pin 1-2 On board 1.8 V Reference (REF3318AIDBZT)
    Pin 2-3 HSEC VREF
  • The DAC VREF Switch (SW6) is a single pole double throw switch that controls the input for the DAC VREF inputs of the AM263x SoC.
    Table 4-20 DAC VREF Switch
    DAC VREF Switch Position Reference Selection
    Pin 1-2 AM263x on-die LDO
    Pin 2-3 Output of VREF Switch
  • The ADC VREF Switch (SW7) contains two single pole double throw switches that control the input for the ADC VREF inputs of the AM263x SoC.
    Table 4-21 ADC VREF Switch
    ADC VREF Switch Position Reference Selection
    Pin 1-2 OPEN - Allow for reference to be AM263x on-die LDO reference
    Pin 2-3 Output of VREF Switch
    Pin 4-5 OPEN - Allow for reference to be AM263x on-die LDO reference
    Pin 5-6 Output of VREF Switch