SPRUJ09D March   2022  – September 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Control Card Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 HSEC 180-pin Control Card Docking Station
    5. 3.5 Compliance
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
      4. 4.1.4 Power Sequence
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
    4. 4.4 JTAG Path Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 RGMII
      2. 5.6.2 PRU-ICSS
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 HSEC Pinout and Pinmux Mapping
  8. 5References
    1. 6.1 References
    2. 6.2 Other TI Components Used in This Design
  9.   Revision History
  10.   A E2 Design Changes
  11.   B E1 HSEC Pinout Table

4.6.1 RGMII

The AM263x Control Card uses one port of RGMII signals to be connected to a 48-pin ethernet PHY (DP83869HMRGZT). The PHY is configured to advertise 1-Gb operation. The ethernet data signals of the PHY are terminated to an RJ45 connector. The RJ45 connector is used on the board for Ethernet 10/100/1000 Mbps connectivity with integrated magnetic and LEDs for link and activity indication.

GUID-20220422-SS0I-NZNC-N7KX-WSNW86K2LXXD-low.png Figure 4-9 RGMII1 Gigabit Ethernet PHY

The Ethernet PHY requires three separate power sources. VDDIO is the 3.3V, system generated supply. There are dedicated LDO's for the 1.1 V and 2.5 V supplies for the Ethernet PHY.

There are series termination resistors on the transmit and receive clock signals located near the AM263x SoC.

The MDIO and Interrupt signals from the SoC to the PHY require 2.2KΩ pull up resistors to the I/O supply voltage for proper operation. The interrupt signal is driven by a GPIO signal that is mapped from the AM263x SoC.

The reset signal for the Ethernet PHY is driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal that is generated by the IO Expander and PORz.

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

GUID-20220422-SS0I-BRPZ-VF2M-Q6FK6ZKNKSZC-low.png Figure 4-10 RGMII1 Gigabit Ethernet PHY Strapping Resistors
Note: RX_D0 and RX_D1 are open rather than pulled down with 2.49KΩ resistors because they are on a 4-level strap resistor mode scheme. All other signals are 2-level strap resistor modes.
Note: Each strapping has an internal pull down resistance of 9KΩ.
Table 4-4 RGMII1 Gigabit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode in CC Function
RX_D0 0 0 PHY address: 0000
RX_D1 0 0
JTAG_TDO/GPIO_1 0 0 RGMII to Copper
RX_D3 0 0
RX_D2 0 0
LED_0 0 0 Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER 0 0
LED_2 0 0
RX_DV 0 0 Port Mirroring Disabled