SPRUJF1C November   2024  – December 2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Component Identification
      3. 1.3.3 Functional Block Diagram
      4. 1.3.4 BoosterPacks
      5. 1.3.5 Device Information
        1. 1.3.5.1 Security
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Standalone Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Tree
      3. 2.2.3 Power Status LEDs
    3. 2.3  Header Information
      1. 2.3.1 OSPI Expansion Connector
      2. 2.3.2 ADC/DAC External VREF Headers
      3. 2.3.3 FSI Header
      4. 2.3.4 EQEP Headers
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  IO Expander
    10. 2.10 Interfaces
      1. 2.10.1  Memory Interfaces
        1. 2.10.1.1 OSPI
        2. 2.10.1.2 Board ID EEPROM
      2. 2.10.2  Ethernet Interface
        1. 2.10.2.1 Ethernet PHY 0 - RGMII2 / PR0_PRU0
        2. 2.10.2.2 Ethernet PHY 1 - RGMII1 / PR0_PRU1
      3. 2.10.3  I2C
        1. 2.10.3.1 Industrial Application LEDs
      4. 2.10.4  SPI
      5. 2.10.5  UART
      6. 2.10.6  MCAN
      7. 2.10.7  SDFM
      8. 2.10.8  FSI
      9. 2.10.9  JTAG
      10. 2.10.10 Test Automation Pin Mapping
      11. 2.10.11 LIN
      12. 2.10.12 ADC and DAC
      13. 2.10.13 EQEP
      14. 2.10.14 EPWM
      15. 2.10.15 USB
    11. 2.11 BoosterPack Headers
      1. 2.11.1 BoosterPack Mode 00: Standard LaunchPad/BoosterPack Pinout
      2. 2.11.2 BoosterPack Mode 01: Servo Motor Control BoosterPacks Mode
      3. 2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode
      4. 2.11.4 BoosterPack Mode 11: C2000 DRVx BoosterPacks Mode
    12. 2.12 Pinmux Mapping
    13. 2.13 Test Points
    14. 2.14 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Compliance
  11. 6Additional Information
    1. 6.1 Revision E1 Appendix
      1. 6.1.1 TA_POWERDOWNz pulled up by VSYS_TA_3V3 which is powered by VSYS_3V3
      2. 6.1.2 USB2.0_MUX_SEL0 pulled up by R355
      3. 6.1.3 MDIO and MDC of PRU0-ICSS0 needs to be routed to both Ethernet PHYs
      4. 6.1.4 AM261_RGMII1_RXLINK and AM261_RGMII2_RXLINK to be connected to GPIO
    2. 6.2 Revision E2 Appendix
      1. 6.2.1 Revision E2 Changes from E1
      2. 6.2.2 Revision E2 Known Limitations
    3. 6.3 Revision A Appendix
      1. 6.3.1 Revision A Changes from E2
      2. 6.3.2 Revision A Errata
    4.     Trademarks
  12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
  13. 8Revision History

2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode

Mode 10 enables BOOSTXL-IOLINKM-8 BoosterPack Connections. The connections and details are shown in the following tables:

Table 2-59 LP-AM261 BoosterPack Mode 10 Mux Settings
BoosterPack Mux Select Net State
BP_MUX_SW_S0 0
BP_MUX_SW_S1 1

Table 2-60 Mode 10: BOOSTXL-IOLINKM-8 BoosterPack (J1/J3)
Selected net BoosterPack Net Name J1 J3 BoosterPack Net Name Selected net
VSYS_3V3_BP 1 21 VSYS_5V0_BP_1
ADC0_AIN1 2 22 GND
UART3_RXD UART3_RXD / SDFM1_D0 3 23 ADC0_AIN6
UART3_TXD 4 24 ADC1_AIN0
PR1_PRU1_GPIO4 5 25 ADC2_AIN0
ADC2_AIN3 ADC2_AIN3 / SDFM1_CLK0 6 26 ADC0_AIN0
PR1_PRU1_GPIO2 SPI0_CLK/PR1_PRU1_GPIO2 7 27 ADC1_AIN4
PR1_PRU1_GPIO11 8 28 ADC2_AIN4
I2C0_SCL 9 29 ADC0_AIN4
I2C0_SDA 10 30 DAC_OUT / ADC1_AIN6 DAC_OUT
Table 2-61 Mode 10: BOOSTXL-IOLINKM-8 BoosterPack (J2/J4)
Selected net BoosterPack Net Name J4 J2 BoosterPack Net Name Selected net
EPWM2_A 40 20 GND
EPWM2_B 39 19 SPI0_CS0 / SDFM0_D2 / PR1_PRU1_GPIO1 PR1_PRU1_GPIO1
EPWM3_A 38 18 PR1_PRU1_GPIO12
EPWM3_B 37 17 SDFM0_D1
EPWM4_A 36 16 PORz
EPWM4_B 35 15 SPI0_D0 / SDFM1_D1 SDFM1_D1 → PR1_PRU1_GPIO7 via pinmux
LIN1_TXD 34 14 SPI0_D1 / PR1_PRU1_GPIO15 PR1_PRU1_GPIO15
PR1_PRU1_GPIO0 LIN1_RXD / PR1_PRU1_GPIO0 33 13 PR1_PRU1_GPIO5
SDFM0_D0 → PR1_PRU1_GPIO10 via pinmux MCAN0_TX / SDFM0_D0 32 12 PR1_PRU1_GPIO9
MCAN0_RX → PR1_PRU1_GPIO16 via pinmux MCAN0_RX / PR1_PRU1_GPIO16 31 11 PR1_PRU0_GPIO0/GPIO1 PR1_PRU0_GPIO0
Table 2-62 Mode 10: BOOSTXL-IOLINKM-8 BoosterPack (J5/J7)
Selected net BoosterPack Net Name J5 J7 BoosterPack Net Name Selected net
VSYS_3V3_BP 41 61 VSYS_5V0_BP_2
ADC1_AIN1 42 62 GND GND
PR1_PRU1_GPIO3 UART3_TXD / PR1_PRU1_GPIO3 43 63 ADC0_AIN2 / GPIO46 GPIO46
PR1_PRU1_GPIO19 UART3_RXD / SDFM1_D2 / PR1_PRU1_GPIO19 44 64 ADC1_AIN2 / PR1_PRU0_GPIO7 PR1_PRU0_GPIO7
SDFM0_CLK0 45 65 ADC2_AIN2 / PR1_PRU0_GPIO8 PR1_PRU0_GPIO8
ADC1_AIN3 46 66 ADC0_AIN5
SPI2_CLK 47 67 ADC1_AIN5 / PR1_PRU0_GPIO1 PR1_PRU0_GPIO1
PR1_PRU1_GPIO6 48 68 ADC2_AIN5 / PR1_PRU0_GPIO2 PR1_PRU0_GPIO2
I2C1_SCL 49 69 DAC_OUT / PR1_PRU1_GPIO0 / PR1_PRU0_GPIO6 / ADC0_AIN3 PR1_PRU0_GPIO6
I2C1_SDA 50 70 DAC_OUT / PR1_PRU1_GPIO9 / GPIO78 / ADC2_AIN6 GPIO78
Table 2-63 Mode 10: BOOSTXL-IOLINKM-8 BoosterPack (J6/J8)
Selected net BoosterPack Net Name J8 J6 BoosterPack Net Name Selected net
EPWM5_A 80 60 GND
EPWM5_B 79 59 SPI2_CS1
EPWM6_A 78 58 SPI2_CS0
EPWM6_B 77 57 PR1_PRU1_GPIO2 / SPI0_CLK / PR1_PRU0_GPIO9 SPI0_CLK → GPIO12 via pinmux
EPWM7_A 76 56 PORz
EPWM7_B 75 55 SPI2_D0
LIN2_TXD 74 54 SPI2_D1
LIN2_RXD 73 53 GPIO6
MCAN1_TX MCAN1_TX / PR1_PRU1_GPIO1 72 52 GPIO124
PR1_PRU0_GPIO9 MCAN1_RX / PR1_PRU0_GPIO9 71 51 GPIO1/PR1_PRU0_GPIO0 GPIO1