DLPS210 Data sheet

DLPS210C March 2021 – September 2025 DLP651NE

PRODUCTION DATA

5.8 Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)

SYMBOL	PARAMETER	TEST CONDITIONS	MIN	MAX	UNIT
LVCMOS
t_r	Rise time ⁽¹⁾	20% to 80% reference points		25	ns
t_f	Fall time ⁽¹⁾	80% to 20% reference points		25	ns
Low Speed Interface (LSIF)
t_r	Rise time ⁽²⁾	20% to 80% reference points		450	ps
t_f	Fall time ⁽²⁾	80% to 20% reference points		450	ps
t_W(H)	Pulse duration high ⁽³⁾	LS_CLK. 50% to 50% reference points	3.1		ns
t_W(L)	Pulse duration low ⁽³⁾	LS_CLK. 50% to 50% reference points	3.1		ns
t_su	Setup time ⁽⁴⁾	LS_WDATA valid before rising edge of LS_CLK (differential)	1.5		ns
t_h	Hold time ⁽⁴⁾	LS_WDATA valid after rising edge of LS_CLK (differential)	1.5		ns
High Speed Serial Interface (HSSI)
t_r	Rise time⁽⁵⁾, Data	from -A1 to A1 minimum eye height specification	50	115	ps
t_r	Rise time⁽⁵⁾, Clock	from -A1 to A1 minimum eye height specification	50	135	ps
t_f	Fall time⁽⁵⁾, Data	from A1 to -A1 minimum eye height specification	50	115	ps
t_f	Fall time⁽⁵⁾, Clock	from A1 to -A1 minimum eye height specification	50	135	ps
t_W(H)	Pulse duration high ⁽⁶⁾	DCLK. 50% to 50% reference points	0.275		ns
t_W(L)	Pulse duration low ⁽⁶⁾	DCLK. 50% to 50% reference points	0.275		ns
t_c	Cycle time ⁽⁶⁾	DCLK	0.625	0.833	ns

(1) See the LVCMOS Rise, Fall Time Slew Rate Figures. Specification is for DMD_DEN_ARSTZ pin (LVCMOS).

(2) See the figure for rise and fall time for LSIF.

(3) See the figure for pulse duration high and low time for LSIF.

(4) See the figure for setup and hold time for LSIF.

(5) See figure for rise and fall time for HSSI.

(6) See the figure for pulse duration high and low and cycle time for HSSI.