DLPU040B October   2016  – March 2023 DLP650LNIR , DLPC410

 

  1.   DLP Discovery 4100 Development Platform User’s Guide
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Welcome
  4. 2Overview
    1. 2.1 The DLP Discovery 4100 Development Platform
    2. 2.2 DLP Discovery 4100 Development Platform Photo
    3. 2.3 Key Components
      1. 2.3.1  Xilinx Virtex 5 APPSFPGA
      2. 2.3.2  DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      3. 2.3.3  DLPA200 - DMD Micromirror Driver
      4. 2.3.4  DLPR410 - Configuration PROM for DLPC410 Controller
      5. 2.3.5  APPSFPGA Flash Configuration PROM
      6. 2.3.6  DMD Connectors
      7. 2.3.7  USB Controller
      8. 2.3.8  50-MHz Oscillator
      9. 2.3.9  DDR2 SODIMM Connector
      10. 2.3.10 Connectors
        1. 2.3.10.1 JTAG Header H1
        2. 2.3.10.2 Mictor Connectors
        3. 2.3.10.3 GPIO Connectors
      11. 2.3.11 Battery
      12. 2.3.12 Power Supplies
        1. 2.3.12.1 J14 Power Connector
        2. 2.3.12.2 J14 Power Connector
        3. 2.3.12.3 REG. 0.9 V
        4. 2.3.12.4 REG. 1.0 V
        5. 2.3.12.5 REG. 1.8 V
        6. 2.3.12.6 REG. 2.5 V
        7. 2.3.12.7 REG. 3.3 V
        8. 2.3.12.8 REG. 12 V
  5. 3Hardware Overview and Setup
    1. 3.1 Getting Started
    2. 3.2 User Connectors and I/O
      1. 3.2.1  J12 Input Power Connector
      2. 3.2.2  J18 Input Power Connector
      3. 3.2.3  J1 USB Connector Pinout
      4. 3.2.4  J3 USB GPIO
      5. 3.2.5  J6 GPIO_A Connector
      6. 3.2.6  J8 DLPC410 Mictor Connector
      7. 3.2.7  J9 USB/APPSFPGA Mictor Connector
      8. 3.2.8  J13 DMD Flex 1 Connector
      9. 3.2.9  J14 DMD Flex 2 Connector
      10. 3.2.10 J15 DDR2 SODIMM Connector
      11. 3.2.11 J16, J17 EXP Connectors
      12. 3.2.12 H1 Xilinx FPGA JTAG Header
    3. 3.3 Configuration Jumpers
      1. 3.3.1 J2 – EXP Voltage Select
      2. 3.3.2 J4 – APPSFPGA Revision Select
      3. 3.3.3 J5 – Shared USB Signal Enable/Disable
      4. 3.3.4 J7 – USB EEPROM Programming Header
      5. 3.3.5 J10 – DLPA200 B Output Enable
    4. 3.4 Switches
      1. 3.4.1 SW1 - APPSFPGA Functional Switches
      2. 3.4.2 SW2 - APPSFPGA Reset
      3. 3.4.3 SW3 - DMD Power Float (Park)
      4. 3.4.4 SW4 - Input Power On/Off
    5. 3.5 Power and Status LEDs
      1. 3.5.1 D1 – USB Connection Indicator
      2. 3.5.2 D2 and D16 – APPSFPGA Done
      3. 3.5.3 D3 and D17 – DLPC410 Done
      4. 3.5.4 D9 – DDC_LED0
      5. 3.5.5 D10 – DDC_LED1
      6. 3.5.6 D11 – VLED0
      7. 3.5.7 D12 – VLED1
    6. 3.6 Test Points
  6. 4Software
    1. 4.1 Overview
      1. 4.1.1 Software Overview
        1. 4.1.1.1 DMD Image Control
        2. 4.1.1.2 Image Commands
    2. 4.2 DLP Discovery 4100 Operation
      1. 4.2.1 Quick Start Guide on Operation
      2. 4.2.2 74
    3. 4.3 Graphical User Interface
      1. 4.3.1 Menu Bar
        1. 4.3.1.1 File Menu
        2. 4.3.1.2 View Menu
        3. 4.3.1.3 DMD Menu
        4. 4.3.1.4 Execution Menu
        5. 4.3.1.5 Test Patterns Menu
        6. 4.3.1.6 Help Menu
      2. 4.3.2 Toolbar
        1. 4.3.2.1 File Menu Buttons
        2. 4.3.2.2 Run, Run Once, Loop Break, Step and Stop Controls
        3. 4.3.2.3 Set Start and End Buttons
        4. 4.3.2.4 Help Button
      3. 4.3.3 Script Commands Window
        1. 4.3.3.1 Load Tab
        2. 4.3.3.2 Reset Tab
        3. 4.3.3.3 Clear Tab
        4. 4.3.3.4 Float Tab
        5. 4.3.3.5 Control Tab
      4. 4.3.4 Status Window
      5. 4.3.5 Script Window
        1. 4.3.5.1 Inserting Commands
        2. 4.3.5.2 Moving Commands
        3. 4.3.5.3 Deleting Commands
    4. 4.4 Script and Status Operations
      1. 4.4.1 Saving Scripts and Statuses
        1. 4.4.1.1 Saving a Script
        2. 4.4.1.2 Saving a Status
      2. 4.4.2 Printing Scripts and Statuses
        1. 4.4.2.1 Printing a Script
        2. 4.4.2.2 Printing a Status
      3. 4.4.3 Opening Scripts and Statuses
      4. 4.4.4 Creating New Scripts and Statuses
        1. 4.4.4.1 Creating a New Script
        2. 4.4.4.2 Creating a New Status
    5. 4.5 DLPC410 Control Window
    6. 4.6 Test Patterns Window
    7. 4.7 About Box
    8. 4.8 Links
  7. 5Related Documentation
  8. 6Appendix
    1. 6.1 Abbreviations and Acronyms
    2. 6.2 Notational Conventions
      1. 6.2.1 Information About Cautions and Warnings
  9. 7Revision History

3.2.9 J14 DMD Flex 2 Connector

Connector J14 provides control and data signals to the DMD Flex 2 connector. This connector is only used for connection to DLP9500 and DLP9500UV DMDs.

Table 3-9 J14 DMD Flex Connector 2
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
1A GND 1B 3.3 V 1C 3.3 V
2C GND 2A DDC_DOUT_C13_DPP 2B DDC_DOUT_C13_DPN
3A GND 3B DDC_DOUT_C11_DPP 3C DDC_DOUT_C11_DPN
4C GND 4A DDC_DOUT_C9_DPP 4B DDC_DOUT_C9_DPN
5A GND 5B DDC_DCLKOUT_C_DPP 5C DDC_DCLKOUT_C_DPN
6C GND 6A DDC_DOUT_C7_DPP 6B DDC_DOUT_C7_DPP
7A GND 7B DDC_DOUT_C5_DPP 7C DDC_DOUT_C5_DPN
8C GND 8A DDC_DOUT_C3_DPP 8B DDC_DOUT_C3_DPN
9A GND 9B DDC_DOUT_C1_DPP 9C DDC_DOUT_C1_DPN
10C GND 10A DAD_B_SCPDO 10B DAD_B_SCPCLK
11A GND 11B DMDSPARE2 11C DMD_B_SCPEN
12C GND 12A MBRST2_15 12B MBRST2_14
13A GND 13B DMD_VCC2 13C DMD_VCC2
14C GND 14A MBRST2_10 14B MBRST2_6
15A GND 15B MBRST2_9 15C MBRST2_7
16C GND 16A MBRST2_13 16B MBRST2_12
17A GND 17B DDC_DOUT_D1_DPP 17C DDC_DOUT_D1_DPN
18C GND 18A DDC_DOUT_D3_DPP 18B DDC_DOUT_D3_DPN
19A GND 19B DDC_DOUT_D5_DPP 19C DDC_DOUT_D5_DPN
20C GND 20A DDC_DOUT_D7_DPP 20B DDC_DOUT_D7_DPN
21A GND 21B DDC_DCLKOUT_D_DPP 21C DDC_DCLKOUT_D_DPN
22C GND 22A DDC_DOUT_D9_DPP 22B DDC_DOUT_D9_DPN
23A GND 23B DDC_DOUT_D11_DPP 23C DDC_DOUT_D11_DPN
24C GND 24A DDC_DOUT_D13_DPP 24B DDC_DOUT_D13_DPN
25A GND 25B DDC_DOUT_D15_DPP 25C DDC_DOUT_D15_DPN
1D GND 1E DDC_DOUT_C15_DPP 1F DDC_DOUT_C15_DPN
2F GND 2D DDC_DOUT_C14_DPP 2E DDC_DOUT_C14_DPN
3D GND 3E DDC_DOUT_C12_DPP 3F DDC_DOUT_C12_DPN
4F GND 4D DDC_DOUT_C10_DPP 4E DDC_DOUT_C10_DPN
5D GND 5E DDC_DOUT_C8_DPP 5F DDC_DOUT_C8_DPN
6F GND 6D DDC_SCTRL_C_DPP 6E DDC_SCTRL_C_DPN
7D GND 7E DDC_DOUT_C6_DPP 7F DDC_DOUT_C6_DPN
8F GND 8D DDC_DOUT_C4_DPP 8E DDC_DOUT_C4_DPN
9D GND 9E DDC_DOUT_C2_DPP 9F DDC_DOUT_C2_DPN
10F GND 10D DDC_DOUT_C0_DPP 10E DDC_DOUT_C0_DPN
11D GND 11E SCPDI 11F DMD_B_RESET
12F GND 12D DMDSPARE0 12E MBRST2_11
13D GND 13E MBRST2_5 13F MBRST2_4
14F GND 14D MBRST2_0 14E MBRST2_3
15D GND 15E MBRST2_2 15F MBRST2_8
16F GND 16D DDC_DOUT_D0_DPP 16E DDC_DOUT_D0_DPN
17D GND 17E DDC_DOUT_D2_DPP 17F DDC_DOUT_D2_DPN
18F GND 18D DDC_DOUT_D4_DPP 18E DDC_DOUT_D4_DPN
19D GND 19E DDC_DOUT_D6_DPP 19F DDC_DOUT_D6_DPN
20F GND 20D DDC_SCTRL_D_DPP 20E DDC_SCTRL_D_DPP
21D GND 21E DDC_DOUT_D8_DPP 21F DDC_DOUT_D8_DPN
22F GND 22D DDC_DOUT_D10_DPP 22E DDC_DOUT_D10_DPN
23D GND 23E DDC_DOUT_D12_DPP 23F DDC_DOUT_D12_DPN
24F GND 24D DDC_DOUT_D14_DPP 24E DDC_DOUT_D14_DPN
25D GND 25E 3.3 V 25F 3.3 V