DLPU094 July   2020 DLP5530S-Q1

 

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6 Description of Device Blocks

This section provides a brief overview of the various blocks of the three chipset components. The quantitative functional safety analysis is done according to these partitions. Partitions for each device are given in Table 1

Table 1. DLPC230S-Q1 Blocks

Block Name Block Function
VGP Video and Graphics Processor. Receives input video data and generates splash images or test patterns. Performs video processing functions such as scaling and color space conversion.
RTP Real-Time Processor. ARM micro-processor core and related memories
RSC Real-Time System Control. Timing control for LEDs, DMD mirror transitions, and ADC measurements. Includes hardware processing blocks and associated memories.
FMT Formatter and Universal Memory Controller. Converts data output from the VGP into single color images that are displayed on the DMD. Includes the SRAM frame buffers. Data is received from the VGP, processed, and stored into the frame buffer. Data is output from the frame buffer to the DMD based on instructions from the RSC.
SSF Clock generation for various clock domains in the DLPC230S-Q1
DDI DMD data interface. High speed interface for outputting data from DLPC230S-Q1 to DMD
FPD OpenLDI input video port
RTP BROM Boot ROM that initiates loading of software from external flash to internal RAM and performs boot tests

Table 2. TPS99000S-Q1 Blocks

Block Name Block Function
AAC ADC control including the TPS99000S-Q1 to DLPC230S-Q1 AD3 interface
CSR Configuration status registers
DEG Deglitching for signals
DTV Data transfer validation. DLPC230S-Q1 to TPS99000S-Q1 SPI port and related functions.
ILM Illumination control
PSC Power state controller
SSF Secondary SPI port for diagnostics
ROM ROM used for storing device trim data

Table 3. DLP5530S-Q1 Blocks

Block Name Block Function
SRAM SRAM cells under micro-mirror layer. Data loaded into SRAM determines state of each mirror.
IO High speed interface that receives the video data from the DLPC230S-Q1
SCTRL Instruction decoder for data received over IO
Reset Ctrl Mirror transition control
LSIF Low speed interface for DMD configuration and mirror reset voltage control