In Shared TDM bus configuration, the ASI buses of multiple TLV320ADCx140/PCMx140-Q1 devices are connected together into a single shared bus, as shown in Figure 3-2.

Figure 3-2 TLV320ADCx140/PCMx140-Q1 Shared TDM Connection Diagram

To avoid multiple devices transmitting output data in the same slot, the TLV320ADCx140/PCMx140-Q1 supports mapping the input channels of a device to a programmable slot using the following registers:

• ASI_CH1 (Page 0x00, Register 0x0B), shown in Figure 3-3
• ASI_CH2 (Page 0x00, Register 0x0C), shown in Figure 3-4
• ASI_CH3 (Page 0x00, Register 0x0D), shown in Figure 3-5
• ASI_CH4 (Page 0x00, Register 0x0E), shown in Figure 3-6

This allows any channel to be mapped to any slot in any order. Furthermore, the TLV320ADCx140/PCMx140-Q1 also supports a secondary SDOUT output (SDOUT2) configured through the GPO_CFG0 register, bit field GPIO1_CFG with value of 0x03, as shown in Figure 3-14. This allows one or more devices outputting slots through two pins: primary output (SDOUT) and secondary output (SDOUT2). The ASI_CHx register bit field CHx_OUTPUT maps a slot to the primary (SDOUT) or secondary output (SDOUT2).

For the example of Figure 3-2, the following I²C script configures the input channels of U1–U4 into slots 0–15 for TLV320ADCx140/PCMx140-Q1, respectively. Note that slots are not assigned to the input channels of each device in sequence to show the flexibility of channel assignments to TDM slots:

w 98 0B 04  # Set U1 Ch1 mapped to slot 4 of SDOUT
w 98 0C 06  # Set U1 Ch2 mapped to slot 6 of SDOUT
w 98 0D 01  # Set U1 Ch3 mapped to slot 1 of SDOUT
w 98 0E 00  # Set U1 Ch4 mapped to slot 0 of SDOUT
w 9A 0B 03  # Set U2 Ch1 mapped to slot 3 of SDOUT
w 9A 0C 05  # Set U2 Ch2 mapped to slot 5 of SDOUT
w 9A 0D 02  # Set U2 Ch3 mapped to slot 2 of SDOUT
w 9A 0E 07  # Set U2 Ch4 mapped to slot 7 of SDOUT
w 9C 0B 08  # Set U3 Ch1 mapped to slot 8 of SDOUT
w 9C 0C 09  # Set U3 Ch2 mapped to slot 9 of SDOUT
w 9C 0D 0A  # Set U3 Ch3 mapped to slot 10 of SDOUT
w 9C 0E 0C  # Set U3 Ch4 mapped to slot 12 of SDOUT
w 9E 0B 0F  # Set U4 Ch1 mapped to slot 15 of SDOUT
w 9E 0C 0D  # Set U4 Ch1 mapped to slot 13 of SDOUT
w 9E 0D 0E  # Set U4 Ch1 mapped to slot 14 of SDOUT
w 9E 0E 0B  # Set U4 Ch1 mapped to slot 11 of SDOUT

This configuration requires that all the devices place their outputs in high-impedance mode, so another device can drive the bus. TLV320ADCx140/PCMx140-Q1 supports driving the output line low or placing it in high-impedance during unused bit clock cycles through the ASI_CFG0 register bit field TX_FILL, shown in Figure 3-7. Setting the TX_FILL places the primary (SDOUT) and secondary output line (SDOUT2) in high-impedance. Note the reset value configures SDOUT and SDOUT2 to drive low during unused bit clock cycles.

TLV320ADCx140/PCMx140-Q1 also supports tri-stating unused channels slots through the ASI_OUT_CH_EN register, as shown in Figure 3-8.

To minimize power consumption by preventing pins from floating, the TLV320ADCx140/PCMx140-Q1 also supports enabling bus-keepers on SDOUT and SDOUT2 outputs. Register ASI_CFG1 controls the bus-keeper on the outputs through the TX_KEEPER bit field, as shown in Table 3-7. This register also controls the length of time SDOUT and SDOUT2 strongly drives the least significant bit (LSB) on the bus. This allows fine control so that two devices do not drive different signals on the same bus line at the same time, avoiding bus contention. For example, the LSB of U2 could be set to transmit on the first half of the bit clock cycle, while the MSB of U3 is driving without any offset. Moreover, selecting TX_KEEPER value of 0x2 or 0x3 adds robustness to the system by ensuring the LSB is latched properly by the host processor, since bus-keepers continue holding the bus with the last value driven. Note that this register also controls the number of bit clocks the most significant bit (MSB) is delayed.

To support a greater number of slots than Equation 1 allows, multiple host processor TDM busses can split the TLV320ADCx140/PCMx140-Q1 devices connected, as shown in Figure 3-10. This connection method not only decreases the bit clock (BCLK) speed by half, but also reduces the load capacitance on the data lines SDIN1 and SDIN2 of the host processor.

Figure 3-10 TLV320ADCx140/PCMx140-Q1 Shared Split TDM Connection Diagram

Another option is to use the secondary output to map slots of a single device to the primary and secondary output. For example, a system with 12 channels, 32-bit data words, and running with a 96-KHz sample rate requires a bit clock of 36.864 MHz (three devices * four channels/device * 32 bit words * 96 kHz), violating the maximum BCLK speed of 25 MHz. Dividing the 12 channels by assigning six channels to a primary bus and six channels to a secondary bus keeps the BCLK under 25 MHz. Since each device has four channels, one device has two channels assigned to the primary bus and two channels assigned to the secondary bus, as shown in Figure 3-11.

Figure 3-11 TLV320ADCx140/PCMx140-Q1 Shared Split TDM With Primary and Secondary Bus Connection Diagram

For the example of Figure 3-11, the following I²C script configures U1, U2, and U3 for Shared TDM with primary and secondary bus.

w 98 0B 00  # Set U1 Ch1 mapped to slot 0 of SDOUT
w 98 0C 01  # Set U1 Ch2 mapped to slot 1 of SDOUT
w 98 0D 02  # Set U1 Ch3 mapped to slot 2 of SDOUT
w 98 0E 03  # Set U1 Ch4 mapped to slot 3 of SDOUT
w 9A 0B 04  # Set U2 Ch1 mapped to slot 4 of SDOUT
w 9A 0C 05  # Set U2 Ch2 mapped to slot 5 of SDOUT
w 9A 22 30  # Set U2 GPIO1 as SDOUT2
w 9A 0D 40  # Set U2 Ch3 mapped to slot 0 of SDOUT2
w 9A 0E 41  # Set U2 Ch4 mapped to slot 1 of SDOUT2
w 9C 22 30  # Set U3 GPIO1 as SDOUT2
w 9C 0B 42  # Set U3 Ch1 mapped to slot 2 of SDOUT2
w 9C 0C 43  # Set U3 Ch2 mapped to slot 3 of SDOUT2
w 9C 0D 44  # Set U3 Ch3 mapped to slot 4 of SDOUT2