SBAA383C January   2020  – January 2024 TLV320ADC3120 , TLV320ADC3140 , TLV320ADC5120 , TLV320ADC5140 , TLV320ADC6120 , TLV320ADC6140

 

  1.   1
  2.   Multiple TLV320ADCx140/PCMx140-Q1 PCM6xx0 Devices With Shared TDM and I2C Bus
  3.   Trademarks
  4. 1Introduction
  5. 2Sharing the Control Bus
  6. 3Sharing the Audio Bus
    1. 3.1 ASI Configuration for Shared TDM
    2. 3.2 ASI Configuration for Daisy Chain TDM
  7. 4Configuring PurePath Console for Multiple TLV320ADCx140/PCMx140-Q1 EVMs
    1. 4.1 Changing the Default I2C Address of the TLV320ADCx140/PCMx140-Q1
    2. 4.2 Launching PurePath Console with Multiple Devices
  8. 5PurePath Console I2C Scripts
    1. 5.1 TLV320ADCx140/PCMx140-Q1 I2C Scripts for Shared TDM
    2. 5.2 TLV320ADCx140/PCMx140-Q1 I2C Scripts for Daisy Chain TDM
  9. 6Revision History

Introduction

For TLV320ADx140 applications requiring more than four channels, multiple TLV320ADCx140/PCMx140-Q1 devices can share a common bus. For systems with up to 16 analog input channels or up to 32 digital microphone inputs, up to four TLV320ADCx140/PCMx140-Q1 devices can share a single control and audio data bus to minimize board routing area. TLV320ADCx140/PCMx140-Q1 supports a control bus using the I2C interface and an audio serial bus using a time-division multiplexed (TDM), Inter-IC Sound (I2S), or Left-justified (LJ) interface. Figure 1-1 shows a diagram of four TLV320ADCx140/PCMx140-Q1 devices sharing the control and audio data buses.

GUID-753271BB-490E-4675-A3DB-7DAEA771A800-low.gif Figure 1-1 Four TLV320ADCx140/PCMx140-Q1 Devices With Shared Control and Audio Data Buses

Each channel of the TLV320ADCx140/PCMx140-Q1 device follows the signal chain shown in Figure 1-2. Each channel of the TLV320ADCx140/PCMx140-Q1 supports an analog differential or single-ended signal or a digital pulse density modulation (PDM) digital microphone. In TLV320ADCx140/PCMx140-Q1 device families, the analog input signal is amplified by a Programmable Gain Amplifier (PGA) and then converted by a high-performance ADC into a digital signal. The PGA gains the input signal to match the full scale of the ADC. The digital signal has a programmable phase calibration to adjust the phase delay of each channel in steps of one modulator clock cycle. This allows the system to match the phase across different channels. The phase-calibrated digital signal is then decimated through a set of linear phase filters or low-latency filters. DC offset is removed from the decimated signal through a Digital High Pass Filter (HPF) with three pre-set cutoff frequencies or a fully programmable cutoff frequency. Note that DC shifts are caused by mismatches in common-mode voltages. The output of the HPF is gain calibrated with 0.1 dB steps and summed with other channels. The gain calibration matches the gain across different channels, particularly if the channels have microphones with varying gain values. The output is then filtered by the Digital Biquad Filters and gained by the volume control.

GUID-0C7B8161-1A24-4FDF-8BFE-86E0FA2EE96C-low.gif Figure 1-2 TLV320ADCx140/PCMx140-Q1 Channel Signal Chain Processing Flow Chart

This application note concentrates on how to configure the TLV320ADCx140/PCMx140-Q1 to share a single control and audio data bus between the devices.