SBAA494A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Processing Blocks of TLV320ADCx120 and PCMx120-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC, DRE, or DRC
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  4. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  5. 4Example Configurations
  6. 5Related Documentation
  7.   A Revision History

2.2.2 Channel Assignment

AGC, DRE, or DRC is only available for analog channels. Analog channels are assigned to input channels 1 and 2. Table 2-4 shows the maximum number of analog channels supported by the device when AGC, DRE, or DRC processing block is enabled.

Table 2-4 Number of Analog Channels Supported with AGC/DRE/DRC Enabled
SAMPLE RATE (kHz)NUMBER OF CHANNELS SUPPORTED WITH AGC/DRE/DRC ENABLED
8 or 7.35 None
16 or 14.72
24 por 22.052
32 or 29.42
48 or 44.12
96 or 88.22
192 or 176.41
384 or 352.8 None
768 or 705.6 None