SBAA520A July   2021  – December 2025 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18 , ADS127L21 , ADS127L21B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Clock Signal
    1. 2.1 Single Clock Buffer
    2. 2.2 Multiple Clock Buffers
    3. 2.3 Clock Jitter
  6. 3 Synchronization
  7. 4 Anti-Alias Filter Group Delay
  8. 5 Reference Voltage
  9. 6 Power Supply Bypassing and Grounding
  10. 7 SPI Daisy-Chain Connection
    1. 7.1 SPI Daisy-Chain Communication
    2. 7.2 System Requirements for SPI Daisy-Chain Configuration
    3. 7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs
  11. 8 Parallel SPI SDO or DRDY Connection for Single Channel ADCs
  12. 9 Determining When New Conversion Data is Available for Single Channel ADCs
  13. 10Frame-Sync Daisy-Chain Connection for Multi-Channel ADCs
    1. 10.1 System Requirements for Frame-Sync Daisy-Chain Configuration
    2. 10.2 Number of Channels in a Frame-Sync Daisy-Chain Connection
  14. 11Summary
  15. 12References
  16. 13Revision History

SPI Daisy-Chain Connection

One challenge with using multiple ADCs is the added complexity of the digital signal routing between ADCs and the host controller. The ADS1x7Lxx family offers a daisy-chain option to streamline the digital signal connections. The single channel ADCs use SPI for both data and configuration. The multichannel ADCs use SPI for configuration only and a frame-sync port for conversion data. The following sections discuss daisy-chain of the SPI port only. Frame-sync daisy-chain is later discussed in System Requirements for Frame-Sync Daisy-Chain Configuration.

The daisy-chain option connects the SPI data output of one ADC into the SPI data input of the next ADC in the chain. These connections effectively link the individual ADC shift registers into one longer-length shift register. From an SPI perspective, the host controller interfaces to the chained devices as a single virtual device. Figure 7-1 illustrates how the individual ADC shift registers emulate a single shift register through the daisy-chain connection.

ADS127L11 ADS117L11 ADS127L21 ADS127L18 ADS127L14 ADS127L21B Daisy-Chain ConceptFigure 7-1 Daisy-Chain Concept

The daisy-chain connection keeps the number of SPI lines to the host controller to four, regardless of the number of ADCs connected in the chain. By comparison, a standard SPI cascade connection requires seven SPI lines to interface to four ADCs.

Figure 7-2 and Figure 7-3 show the required SPI signals for a standard SPI cascade connection and a daisy-chain connection, respectively. If using either standard SPI cascade or daisy-chain connection, additional control lines are potentially necessary. Additional control lines are often used for ADC synchronization (START), ADC reset (RESET), and in the case of single channel ADCs, data-ready output (DRDY).

ADS127L11 ADS117L11 ADS127L21 ADS127L18 ADS127L14 ADS127L21B Standard SPI Cascade ConnectionFigure 7-2 Standard SPI Cascade Connection
ADS127L11 ADS117L11 ADS127L21 ADS127L18 ADS127L14 ADS127L21B Daisy-Chain SPI ConnectionFigure 7-3 Daisy-Chain SPI Connection