11 Summary

Data acquisition systems commonly require multiple ADCs operating in parallel. Designing these multi-device systems requires special consideration regarding the clock signal, synchronization, and voltage reference. The clock signal must be low jitter and routed to the ADCs using recommended best practices. Following these guidelines minimizes clock jitter noise and reduces interference from other clock signals. Synchronizing the ADCs after power-on and after the ADC configuration is changed by asserting the START pin high on the clock signal falling edge is important. The reference voltage ground must be tied at a single point at the reference voltage ground terminal. Daisy-chaining the ADCs can be effective in simplifying the number of SPI I/O connections and frame-sync I/O connections between ADCs and the host controller. Parallel SDO/DRDY connections increase data throughput for single-channel ADCs by providing the ability to clock output data in parallel. Parallel DOUT connections for frame-sync multichannel ADCs also increase data throughput by providing the ability to clock output data in parallel.