In this architecture, a single-channel voltage DAC is connected to a de-multiplexer with hold capacitor on each output channel. The MUX switch in addition to the hold capacitor acts as track and hold circuit. If the DAC output is sequentially changed in synchronicity with the multiplexer, separate static or dynamic outputs can be generated from a single channel DAC output.

This is a cost effective implementation, but requires careful design as the settling time of the DAC output, as well as the MUX leakage puts the minimum and maximum limits of the MUX hold time and scanning frequency. These tradeoff are well explained in Multi-Channel Analog Output Module With Multiplexed Single-Channel DAC for PLCs reference design.

Figure 4-2 Block diagram for track and hold multiplexed output architecture

Both low voltage DACs like DAC80501 (16b) ,DAC70501 (14b), DAC60501 (12b) or high voltage DACs like DAC8760 (16b) or DAC7760 (12b) can be used in this architecture. When low voltage DACs is used, the necessary gain is fulfilled by the output buffer. This architecture uses voltage and current buffers like the previous architecture, which are described in a later section.