SBAA669 February   2025 ADC3548 , ADC3549 , ADC3568 , ADC3569 , ADC3648 , ADC3649 , ADC3664 , ADC3668 , ADC3669

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AAF Tradeoffs at Low Frequency and Low Sampling Rate
  6. 3AAF Tradeoffs at Low Frequency and Higher Sampling Rate
  7. 4The Power of the ADC's Integrated DDC
  8. 5Summary
  9. 6References

4 The Power of the ADC's Integrated DDC

With smaller IC process geometries more readily available, it is now possible to design ADCs that are both high-speed (MSPS) and rich in digital features, similar to the GSPS converters currently on the market. The digital down converter (DDC) is integral to these added digital features, allowing users to improve the digital backend processing in numerous ways. With proper frequency planning, see FREQ-DDC-FILTER-CALC RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator, the user can sample the signal, employ the integrated DDC within the ADC, and move only a portion of the bandwidth of interest digitally with little to no analog filtering.

For example, using the ADC3669, 16bit, 500MSPS ADC, we can configure the ADC to sample only a portion of the band, as outlined in Figure 4-1, so that HD2 and HD3 harmonics fall out of band. This first example shows an undecimated signal, when the ADC is in DDC Bypass mode. Ignoring the highlighted region, you can see the undesired harmonics are in band, and are negatively affecting the ADC’s dynamic range performance.

ADC3669, 500MSPS ADC in Full DDC Bypass ModeFigure 4-1 ADC3669, 500MSPS ADC in Full DDC Bypass Mode

Next is an example of an FFT capture using the same ADC3669 device in Real Decimation mode, with a complex decimation factor of 8. As seen, the undesired harmonic spurs now fall out of band, and are effectively filtered out in the digital domain. This improves our performance in two dimensions; a +6dB improvement in SNR, this is due to the processing gain in Equation 1 or in Equation 2.

Equation 1. 10 × log 10 F s 2 × B W
Equation 2. S N R   = 6 . 02 × N + 1 . 76 d B + 10 × log 10 F s 2 × B W

Where: N = Number of ADC bits

Fs = ADC sampling frequency

BW = bandwidth of interest within the Nyquist zone

As well as removing the undesired harmonic spurs (HD2/HD3) to fall out of band, yielding an SFDR of -85dB or better. Thank you DDC! Check out Figure 4-2 and Addressing High Data-Throughput Challenges, Chase Wood, Embedded Computing Design, Unlocking RF Potential with Down converters, Chase Wood, Embedded Computing Design , and Analyzing High-Bandwidth Spectrum Clusters, Chase Wood, Embedded Computing Design for a deep dive on decimation basics and tradeoffs.

ADC3669, 500MSPS With Complex Decimation-by-8 EnabledFigure 4-2 ADC3669, 500MSPS With Complex Decimation-by-8 Enabled