SBAA669 February   2025 ADC3548 , ADC3549 , ADC3568 , ADC3569 , ADC3648 , ADC3649 , ADC3664 , ADC3668 , ADC3669

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AAF Tradeoffs at Low Frequency and Low Sampling Rate
  6. 3AAF Tradeoffs at Low Frequency and Higher Sampling Rate
  7. 4The Power of the ADC's Integrated DDC
  8. 5Summary
  9. 6References

1 Introduction

With the advent of high-speed MSPS ADCs now climbing onto smaller process geometries, manufacturers are achieving 65nm and lower. This allows for inherent digital features such as the DDC, digital down converter, more commonly seen in GSPS ADCs IC designs, to be employed in the lower sampling rate brethren. This application note reveals how spurious performance can be improved significantly in your next MSPS converter signal chain design. Anti-aliasing filter requirements commonly used in many signal chain applications versus the true power of the inherent digital features, such as the DDC can also be explored. Using either, or a combination of both, techniques radically improves spurious free dynamic range in the next generation of MSPS converters on the market.