SBAS683C August   2014  – August 2026 ADS1120-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Clock Source
      5. 8.3.5  Modulator
      6. 8.3.6  Digital Filter
      7. 8.3.7  Output Data Rate
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Power Supplies
      14. 8.3.14 Temperature Sensor
        1. 8.3.14.1 Converting From Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready ( DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011xb)
        2. 8.5.3.2 START/SYNC (0000 100xb)
        3. 8.5.3.3 POWERDOWN (0000 001xb)
        4. 8.5.3.4 RDATA (0001 xxxxb)
        5. 8.5.3.5 RREG (0010 rrnnb)
        6. 8.5.3.6 WREG (0100 rrnnb)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]
        2. 8.6.2.2 Configuration Register 1 (Address = 01h) [reset = 00h]
        3. 8.6.2.3 Configuration Register 2 (Address = 02h) [reset = 00h]
        4. 8.6.2.4 Configuration Register 3 (Address = 03h) [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudocode Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Ramp Rate
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet the requirements discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 8-2 cannot swing closer to the supplies (AVSS and AVDD) than 200mV. If the outputs OUTP and OUTN are driven to within 200mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition the output voltages must meet Equation 6 and Equation 7:

Equation 6. A V S S + 0.2 V ≤ V O U T N
Equation 7. VOUTP≤AVDD-0.2V

Translating the requirements of Equation 6 into requirements referred to the PGA inputs (AINP and AINN) is beneficial because no direct access to the outputs of the PGA exists. The PGA employs a symmetrical design, therefore the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 8-3.

ADS1120-Q1 PGA Common-Mode Voltage Figure 8-3 PGA Common-Mode Voltage

Equation 8 calculates the common-mode voltage:

Equation 8. V C M = V A I N P + V A I N N 2 = V O U T P + V O U T N 2

Equation 9 and Equation 10 calculates the voltages at the PGA inputs (AINP and AINN):

Equation 9. V A I N P = V C M + V I N 2
Equation 10. V A I N N = V C M - V I N 2

Equation 11 and Equation 12 calculates the output voltages (VOUTP and VOUTN):

Equation 11. V O U T P = V C M + G a i n 2 × V I N
Equation 12. V O U T N = V C M - G a i n 2 × V I N

Equation 13 and Equation 14 calculate the requirements for the input common-mode voltage range using the requirements for the output voltages of amplifiers A1 and A2 (Equation 6) and the values from Equation 11 and Equation 12:

Equation 13. V C M M I N ≥ A V S S + 0.2 V + G a i n 2 × V I N M A X
Equation 14. V C M M A X ≤ A V D D - 0.2 V - G a i n 2 × V I N M A X

To calculate the minimum and maximum common-mode voltage limits, use the maximum differential input voltage (VINMAX) that occurs in the application. VINMAX can be less than the maximum possible FS value.

In addition to Equation 13, the minimum VCM must also meet Equation 15 because of the specific design implementation of the PGA.

Equation 15. V C M M I N ≥ A V S S + A V D D - A V S S 4

Figure 8-4 and Figure 8-5 show the common-mode voltage limits for AVDD = 3.3V and AVSS = 0V, with gain = 1 and gain = 16, respectively.

ADS1120-Q1 Common-Mode Voltage Limits (Gain = 1)
AVDD = 3.3V
Figure 8-4 Common-Mode Voltage Limits
ADS1120-Q1 Common-Mode Voltage Limits (Gain = 16)
AVDD = 3.3V
Figure 8-5 Common-Mode Voltage Limits

The following discussion explains how to apply Equation 13 through Equation 15 to a hypothetical application. The setup for this example is AVDD = 3.3V, AVSS = 0V, and gain = 16, using an external reference,
VREF = 2.5V. The maximum possible differential input voltage VIN = (VAINP – VAINN) that can be applied is then limited to the full-scale range of FSR = ±2.5V / 16 = ±0.156V. Consequently, Equation 13 through Equation 15 yield an allowed VCM range of 1.45V ≤ VCM ≤ 1.85V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to VINMAX = ±0.1V, for example, then this reduced input signal amplitude relaxes the VCM restriction to 1.0V ≤ VCM ≤ 2.3V.

In the case of a fully-differential sensor signal, each input (AINP, AINN) can swing up to ±50mV around the common-mode voltage (VAINP + VAINN) / 2, which must remain between the limits of 1.0V and 2.3V. The output of a symmetrical Wheatstone bridge is an example of a fully-differential signal. Figure 8-6 shows a situation where the common-mode voltage of the input signal is at the lowest limit. VOUTN is exactly at 0.2V in this case. Any further decrease in common-mode voltage (VCM) or increase in differential input voltage (VIN) drives VOUTN below 0.2V and saturates amplifier A2.

ADS1120-Q1 Example Where VCM is at Lowest Limit Figure 8-6 Example Where VCM is at Lowest Limit

In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in the RTD Measurement section), where the negative input is held at a constant voltage other than 0V and only the voltage on the positive input changes. To measure a pseudo-differential signal, bias the negative input in this example at a voltage between 0.95V and 2.25V. The positive input can then swing up to VINMAX = 100mV above the negative input. In this case, the common-mode voltage changes at the same time the voltage on the positive input changes. While the input signal swings between 0V ≤ VIN ≤ VINMAX, the common-mode voltage swings between VAINN ≤ VCM ≤ VAINN + VINMAX / 2. The requirements for the entire signal range are met if the common-mode voltage requirements for the maximum input voltage VINMAX are satisfied.

Figure 8-7 and Figure 8-8 show examples of both fully-differential and pseudo-differential signals, respectively.

ADS1120-Q1 Fully-Differential Input Signal
Figure 8-7 Fully-Differential Input Signal
ADS1120-Q1 Pseudo-Differential Input Signal
Figure 8-8 Pseudo-Differential Input Signal
Note:

Remember, common-mode voltage requirements with PGA enabled (Equation 13 to Equation 15) are as follows:

  • VCMMIN ≥ AVSS + ¼ × (AVDD – AVSS)
  • VCMMIN ≥ AVSS + 0.2V + ½ × Gain × VIN (MAX)
  • VCMMAX ≤ AVDD – 0.2V – ½ × Gain × VIN (MAX)