When connecting multiple ADS1120-Q1 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective device, DOUT/DRDY enters a 3-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data are available if CS is high, regardless of the DRDYM bit setting in the configuration register. Only the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even when CS is high.

In some cases the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated and thus the amount of channels must be limited. Therefore, evaluate when a new conversion of one of the devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of the DOUT/DRDY pin. When CS goes low, the DOUT/DRDY pin immediately drives either high or low, provided that the DRDYM bit is configured to 1b. If the DOUT/DRDY line drives low, when CS is taken low, new data are currently available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that DOUT/DRDY is high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY is taken high, send 16 additional SCLKs with DIN held low after each data read operation. DOUT/DRDY reads low during the first eight SCLKs after the conversion result is read, and reads high during the following eight SCLKs, as shown in Figure 8-31. Alternatively, valid data can be retrieved from the device at any time without concern of data corruption by using the RDATA command.

Figure 8-31 Example of Taking DOUT/DRDY High After Reading a Conversion Result