SBAU338B
October 2019 – September 2025
1
Description
Features
4
1
EVM Overview
1.1
Caution and Warnings
1.2
Introduction
1.3
Kit Contents
1.4
Specifications
1.5
Device Information
2
Hardware
2.1
Recommended Test Environment
2.2
Required Hardware
2.3
Hardware Setup
2.3.1
AFE79xx EVM and TSW14J58 EVM Connections
2.3.2
Power Supply Setup
3
Software
3.1
Required Software
3.1.1
Software Installation Sequence
3.2
Latte Overview
3.2.1
Latte User Interface
3.2.2
Useful Latte Short-Cuts
4
Implementation Results
4.1
AFE79xxEVM Configuration
4.1.1
Connect Latte to Board
4.1.2
Compile Libraries
4.1.3
Program AFE79xx EVM
4.1.4
TXDAC Evaluation
4.1.5
RXADC and FBADC Evaluation
4.2
AFE79xxEVM Configuration Modifications
4.2.1
Data Converter Clocks Settings
4.2.2
Data Rate and JESD Parameters
4.2.3
Steps to Modify NCO
4.2.4
Steps to Modify DSA
5
Hardware Design Files
5.1
Schematics
5.2
PCB Layouts
5.3
Bill of Materials (BOM)
6
Additional Information
6.1
Status Check and Troubleshooting Guidelines
6.1.1
AFE79xx EVM Status Indicators
6.1.2
TSW14J58EVM Status Indicators
Trademarks
7
Revision History
Features
Onboard FPGA mezzanine card (FMC) connector
Includes complete power management circuitry
Onboard clock generator to provide reference clocks and SYSREF
Internal PLL/VCO to generate DAC/ADC clocks
Optional external CLK at DAC or ADC rate
SerDes data interface:
JESD204B and JESD204C compliant
8 SerDes transceivers up to 29.5Gbps
8b/10b and 64b/66b encoding
12-bit, 16-bit, 24-bit, and 32-bit resolution
Subclass 1 multi-device synchronization