SBAU430 April   2025 DAC39RF12

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents (Required Equipment)
  6. 2Hardware
    1. 2.1 Setup Procedure
      1. 2.1.1  Installing the DAC39RF12EVM Configuration GUI Software
        1. 2.1.1.1 Installing & Setting Up Vivado Lab Tools
      2. 2.1.2  Connect the DAC39RF12EVM and TSW14J59EVM
      3. 2.1.3  Connect the Power Supplies to the Boards (Power Off)
      4. 2.1.4  Connect the Spectrum Analyzer to the EVM
      5. 2.1.5  Turn On the TSW14J59EVM Power and Connect to the PC
      6. 2.1.6  Turn On the DAC39RF12EVM Power Supplies and Connect to the PC
      7. 2.1.7  Turn On the Signal Generators
      8. 2.1.8  Launching the DAC39RF12EVM GUI and Programing the DAC EVM - JMODE 0
      9. 2.1.9  Launching the DAC39RF12EVM GUI and Programing the DAC EVM - JMODE 1
      10. 2.1.10 Launching the DAC39RF12EVM GUI and Programing the DAC EVM - JMODE 3
    2. 2.2 Evaluation Board Details: Analog Outputs
    3. 2.3 FMC Signal Routing
  7. 3References
    1. 3.1 Trademarks

2.1.4 Connect the Spectrum Analyzer to the EVM

Connect a spectrum analyzer to the Aoutp (J1) SMA connector of the DAC39RF12EVM .

Note:
  1. The FPGA REF clock frequency can be obtained from the DAC39RF12EVM GUI once the DAC39RF12EVM GUI is configured to the desired JMODE mode and clock rate. The Reference Clock frequency required by the EVM is displayed on first page of the GUI shown in Figure 1-1.
  2. Make sure that the DEVCLK and Reference clock sources are frequency-locked using a common 10MHz reference to for functionality.
  3. Do not turn on the RF output of any signal generator at this time.
  4. In all of these examples the FPGA REF clock = 160MHz, the DAC sampling clock = 10.24GHz.