SBAU466B October   2024  – October 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Equipment
    2. 2.2 Setup Procedure
      1. 2.2.1  Installing the High Speed Data Converter (HSDC) Pro Software
      2. 2.2.2  Installing the DAC39RF10EVM Configuration GUI Software
      3. 2.2.3  Connect the TRF1108-DAC39RFEVM and TSW14J59EVM
      4. 2.2.4  Connect the Power Supplies to the Boards (Power Off)
      5. 2.2.5  Connect the Spectrum Analyzer to the EVM
      6. 2.2.6  Turn On the TSW14J59EVM Power and Connect to the PC
      7. 2.2.7  Turn On the TRF1108-DAC39RFEVM Power Supplies and Connect to the PC
      8. 2.2.8  Turn On the Signal Generator RF Outputs
      9. 2.2.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
      10. 2.2.10 Programming the NCO
        1. 2.2.10.1 SPIDAC (NCO only) Operation
      11. 2.2.11 Launch the HSDC pro Software and Load the FPGA Image to the TSW14J59EVM
    3. 2.3 Device Configuration
      1. 2.3.1 Supported JESD204C Device Features
      2. 2.3.2 Tab Organization
      3. 2.3.3 Register Map and Console Control
    4. 2.4 Troubleshooting the TRF1108-DAC39RFEVM
    5. 2.5 Customizing the EVM for Optional Clocking Support
      1. 2.5.1 LMX->DACCLK | LMX/LMK-> FPGA Option (Default)
      2. 2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 2.5.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    6. 2.6 Signal Routing
    7. 2.7 Jumpers and LEDs
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5References
    1. 5.1 Technical Reference Documents
    2. 5.2 TSW14J59EVM Operation
  11. 6Revision History

1.1 Introduction

This evaluation board also includes the following important features:

  • The LMX1204 clock chip distributes the DAC sampling clock
  • The LMK04828, clock generator generates SYSREF and FPGA reference clocks for the high-speed serial interface
  • Transformer-coupled clock input network to test the DAC performance with an external low-noise clock source
  • High-speed serial data output over a high pin count FMC+ interface connector
Note: To improve signal routing quality, serial lane polarity is inverted with respect to the standard FMC VITA-57 signal mapping. Signal mapping and polarity is shown in Table 2-6).
TRF1108-DAC39RFEVM EVM Orientation Figure 1-1 EVM Orientation

TRF1108-DAC39RFEVM can be used with the TSW14J59EVM board (pattern generator board). TSW14J59EVM can quickly and easily interface with the TRF1108-DAC39RFEVM.

Note: For now, only 64b/66b encoding modes from serializer/deserializer (SerDes) data rate from 6Gbps to 12.8Gbps are supported by the TSW14J59EVM. The support for 8b/10b modes and lower SerDes rate is added to future release of HSDC pro software.

The High-Speed Data Converter Pro (HSDC Pro) software is used to communicate with the TSW14J59EVM and is used to generates the data pattern for DAC39RF10.

The TSW14J59EVM takes the generated data pattern, encodes the data, stores the data in memory, and then sends to TRF1108-DAC39RFEVM through the high-speed serial data link (JESD interface).

With proper hardware selection in the HSDC Pro software, the TSW14J59EVM is automatically configured to support a wide range of operating speeds of the TRF1108-DAC39RFEVM, but there is a possibility the TSW14J59EVM board does not cover the full operating range of the DAC device.

CAUTION:
TRF1108-DAC39RFEVM
Hot surface. Contact can cause burns. Do not touch.