SBOA367B December 2019 – June 2022 TLV9001 , TLV9002 , TLV9004 , TLV9051 , TLV9052 , TLV9054 , TLV9061 , TLV9062 , TLV9064
This circuit behaves like a single stage high pass filter where the maximum level is set by the capacitor divider formed by CID, the CCM parasitic capacitors, and CSHDN. The pole frequency is set by the RC combination of the parallel capacitances of CCM, CID, and CSHDN with RLoad. The effect of RSHDN is negligible assuming RSHDN is much greater than RLoad, as is the case here.
CID, CCM, CSHDN, and RSHDN cannot be changed as they are intrinsic values of the device. Thus, the output load must be modified in order to change the pole frequency. This can be verified through TINA-TI SPICE simulation. Again, the TLV9002S data sheet is used for the values of CID, CCM, CSHDN, and RSHDN with a 10-kΩ load.
Figure 6-6 shows the frequency response of this circuit. In this example scenario, input signals will be attenuated at about –15 dB for frequencies beyond the bandwidth of the TLV9002. However, this may not be the case for higher bandwidth devices. For such devices, high frequency noise can couple through to the output and, depending on the application, impact downstream circuitry.