SBOA626 December 2025 OPA187 , OPA192 , OPA202 , OPA320
Figure 1-1 illustrates an op amp circuit with stability issues and an equivalent control system diagram. Control system diagrams and control system terminology are often used in op amp stability discussions because much of the literature for stability was developed for control systems and then applied to op amp circuits. The inputs of the op amp correspond to the following blocks for the summing block of the control system:
The circuit in Figure 1-1 is unstable because of the delay elements in the feedback network. The delay elements are simply RC low pass filters. A low pass filter naturally has a group delay or phase shift. The reason that this feedback delay causes instability can be understood by thinking of the op amp circuit as a control system. The input summing block of the op amp senses the output signal through the feedback network. The output of the summing block is the error signal. In this example, the target for VOUT is 2 × VIN. When VOUT = 2VIN the error signal is zero. When the output is too high (VOUT > 2 × VIN), the error signal is negative and the op amp tries to drive the output downward. Similarly, when the output is too low (VOUT < 2 × VIN), the error signal is positive and the op amp tries to drive the output upward to cancel the error. Thus, the output is a constant value of VOUT = 2VIN when the system is in equilibrium.
However, the functionality of the system assumes the feedback signal (VFB) is not significantly delayed. If VFB is significantly delayed, the op amp can incorrectly identify the output as going upward when the output is actually going downward. This outcome creates an error signal with the wrong polarity, which drives the output in the wrong direction. Instability of the op amp is caused by this delay in the feedback signal.
Many engineers see the circuit shown in Figure 1-1 and understand that the feedback delay is a problem, and the general assumption is no one intentionally designs such an impractical circuit. However, the circuit shown in Figure 1-1 is frequently inadvertently created by the internal open-loop output impedance (RO or ZO), the input capacitance of the op amp, and any parasitic PCB capacitance (CIN = CCM+CPCB). Figure 1-2 shows the circuit redrawn to emphasize how the delay elements are created in a practical op amp circuit.