SBOSAK8 March   2025 INA950-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Amplifier Input Common-Mode Range
      2. 6.3.2 Input-Signal Bandwidth
      3. 6.3.3 Low Input Bias Current
      4. 6.3.4 Low VSENSE Operation
      5. 6.3.5 Wide Fixed-Gain Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 Unidirectional Operation
      2. 6.4.2 High Signal Throughput
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 RSENSE and Device Gain Selection
      2. 7.1.2 Input Filtering
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Overload Recovery With Negative VSENSE
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.1.2 Input Filtering

Note:

Input filters are not required for accurate measurements using the INA950-SEP, and use of filters in this location is not recommended. If filter components are used on the input of the amplifier, follow the guidelines in this section to minimize the effects on performance.

Based strictly on user design requirements, external filtering of the current signal can be desired. The initial location that can be considered for the filter is at the output of the current-sense amplifier. Although placing the filter at the output satisfies the filtering requirements, this location changes the low output impedance measured by any circuitry connected to the output voltage pin. The other location for filter placement is at the current-sense amplifier input pins. This location also satisfies the filtering requirement, but the components must be carefully selected to minimally impact device performance. Figure 7-1 shows a filter placed at the input pins.


INA950-SEP Filter at Input Pins
Figure 7-1 Filter at Input Pins

External series resistance provides a source of additional measurement error, so keep the value of these series resistors to 10Ω or less to reduce loss of accuracy. The internal bias network shown in Figure 7-1 creates a mismatch in input bias currents (see Section 5.6) when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, a mismatch is created in the voltage drop across the filter resistors. This voltage is a differential error voltage in the shunt resistor voltage. In addition to the absolute resistor value, mismatch resulting from resistor tolerance can significantly impact the error because this value is calculated based on the actual measured resistance.

Use Equation 4 to calculate the measurement error expected from the additional external filter resistors, and use Equation 5 to calculate the gain error factor.

Equation 4.
INA950-SEP
Equation 5.
INA950-SEP

Where:

  • RIN is the external filter resistance value.
  • R1 is the INA950-SEP input resistance value specified in Table 6-1.
  • RB in the internal bias resistance, which is 6600Ω ± 20%.

The gain error factor, shown in Equation 4, can be calculated to determine the gain error introduced by the additional external series resistance. Equation 4 calculates the deviation of the shunt voltage, resulting from the attenuation and imbalance created by the added external filter resistance. Table 7-2 provides the gain error factor and gain error for several resistor values.

Table 7-2 Example Gain Error Factor and Gain Error for 10Ω External Filter Input Resistors

DEVICE (GAIN)

GAIN ERROR FACTOR

GAIN ERROR (%)

20

0.99658

–0.34185