The first filter located at the input of the PGA (see Figure 8-9) helps reduce electromagnetic interference (EMI) and radio frequency interference (RFI), high-frequency, extrinsic noise. Customize this filter as per the application bandwidth and anti-aliasing requirements.

The second filter is provided by C_FB in parallel with the PGA 6.67kΩ feedback resistors. The PGA resistors are ±15% absolute tolerance, as such, consider the effect of the tolerance on the filter cutoff frequency. C_FB = 33pF results in a filter cutoff frequency of 723kHz. On the high side of the resistor tolerance, the filter frequency changes to 629kHz. The device allows for flexibility to modify the C_FB capacitor value to adjust bandwidth, with a trade-off on the broadband noise of the circuit.

The third filter placed at the ADS8860 inputs works as a charge reservoir filter to drive the SAR ADC. The charge kickback filter reduces the instantaneous charge demand of the amplifier, maintaining low distortion that otherwise potentially degrades because of incomplete ADC sample-and-hold settling. The RC filter combination (R_FIL, C_DIFF) is tuned for ADC sample-and-hold settling and total harmonic distortion (THD) performance, while maintaining stability of the PGA. High-grade C0G capacitors are used everywhere in the signal path for the low distortion properties.

The PGA848 front end, accounting for all three filters, provides a nominal f_–3dB bandwidth of 160kHz. On the high side of the internal 6.67kΩ feedback resistor tolerance, the PGA848 f_–3dB bandwidth changes to 157kHz. However, the circuit maintains –0.1dB flatness to 25kHz (derived from simulation of the cascaded filter stages).

The ADS8860 requires a full-scale input in the range of 0V to the 5V ADC reference. The PGA848 REF pin is set to a nominal voltage of 2.5V to shift the signal to the ADC midscale voltage.

Generate the PGA848 REF voltage by feeding the REF6250 5V reference through a 10kΩ-to-10kΩ precision voltage divider implemented with ±0.05% tolerance, low-drift ±5ppm/°C resistors. Drive the PGA848 REF pin with a low-impedance source. Use an op amp such as the OPA387 as a buffer to drive the REF pin.

The OPA387 buffer is configured in a dual-feedback configuration to provide stability while driving the REF pin and 22nF bypass capacitor. R_ISO is a 20Ω isolation resistor that provides separation of two feedback paths for optimized stability. The first feedback path through the feedback resistor, R_F = 2kΩ, connected directly to the REF pin. The second feedback path is through the feedback capacitor, C_F = 2200pF, connected to the output of the op amp. The circuit provides a loop gain phase margin of 86°. The noninverting input of the OPA387 buffer has a low-pass filter with R = 1kΩ, C = 10nF to reduce the resistive divider thermal noise. Using any other load capacitance requires recalculation of the stability components: R_F, C_F, and R_ISO. If modifying the REF bypass capacitance, verify the circuit is stable with simulation using the OPA387 TINA-TI model (or PSpice®-for-TI model). Confirm the circuit provides more than 60° of phase margin.

Performance and SNR are function of the system bandwidth. Setting the system bandwidth to fit application requirements enables higher performance. In the previous example, reducing the PGA bandwidth to 23kHz by setting C_FB = 1nF improves the SNR at higher gains by almost 12dB as shown in Table 8-3.