SBOSAN4A August   2025  – December 2025 PGA848

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Using the Output Difference Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Linear Operating Input Range
      2. 8.1.2 Current Consumption with Differential Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 Driving a Single-Ended Input SAR ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at TA = 25 °C, VS = VSOUT = ±15V, VICM = 0V, VREF = 0V, RL = 10kΩ connected to ground, and G = 1V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage (RTI) G = 5 to 100 ±50 ±300 µV
G = 0.5, 1, 2 ±100 / G ±700 / G
Offset voltage drift RTI) TA = –40°C to +125°C G > 1 ±0.1 ±1.0 µV/°C
G = 0.5, 1 ±0.2 ±2.0
PSRR Power-supply rejection ratio ±4.5V ≤ VS ≤ ±18V, RTI G = 0.5 108 124 dB
G = 1 114 128
G = 2 118 130
G ≥ 5 120 134
zid Differential input impedance 100 || 1 GΩ || pF
 TA = –40°C to +125°C 10 || 1
zic Common-mode input impedance 100 || 4.4
VICM Common-mode input voltage VS = ±4.5V to ±18V, TA = –40°C to +125°C (VS–) + 3 (VS+) – 3 V
VIN Differential input voltage(1) –16 +16 V
CMRR Common-mode rejection ratio At dc to 60Hz,
VICM = ±10V,
TA = –40°C to +125°C,
RTI		 G = 0.5 69 82 dB
G = 1 75 88
G = 2 80 94
G = 5 88 100
G = 10 95 106
G = 20 100 112
G = 50 108 116
G = 100 116 124
BIAS CURRENT
IB Input bias current ±0.5 ±2 nA
TA = –40°C to +125°C ±1 ±3.6
Input bias current drift TA = –40°C to +125°C ±5 pA/°C
IOS Input offset current ±0.5 ±1 nA
TA = –40°C to +125°C ±1 ±2
Input offset current drift TA = –40°C to +125°C ±5 pA/°C
NOISE VOLTAGE
eNI Voltage noise density (RTI) f = 1kHz G = 100 8.5 nV/√Hz
G = 50 8.5
G = 20 8.5
G = 10 8.5
G = 5 10.5
G = 2 19.5
G = 1 39.5
G = 0.5 78.5
ENI Voltage noise (RTI) fB = 0.1Hz to 10Hz G = 100 0.29 µVPP
G = 50 0.29
G = 20 0.29
G = 10 0.29
G = 5 0.29
G = 2 0.47
G = 1 0.78
G = 0.5 1.55
iN Input current noise density f = 1kHz 0.19 pA/√Hz
IN Input current noise fB = 0.1Hz to 10Hz 7.5 pAPP
GAIN
Gain 0.5 100 V/V
GE Gain error G = 0.5, 1, 2 ±0.005 ±0.035 %
G = 5, 10, 20, 50 ±0.015 ±0.045
G = 100 ±0.025 ±0.055
Gain drift TA = –40°C to +125°C G = 2 ±0.05 ±1 ppm/°C
G ≠ 2 ±0.2 ±2
Gain nonlinearity G = 0.5, VOUT = 8V
G = 1 to 20, VOUT = 10V		 ±2 ±6 ppm
G = 50, 100, VOUT = 10V ±15 ±35
TA = –40°C to +125°C,
G = 0.5, VOUT = 8V
G = 1 to 100, VOUT = 10V		 G ≤ 20 ±3 ±6
G = 50, 100 ±15 ±35
OUTPUT
VOUT Output voltage(2) No load, VSOUT = ±2.25V VLVSS + 0.1 VLVDD – 0.1 V
RL = 10kΩ VSOUT = ±2.25V VLVSS + 0.2 VLVDD – 0.2
VSOUT = ±18V VLVSS + 0.4 VLVDD – 0.4
CL Load capacitance  Stable operation for capacitive load 100 pF
ISC Short-circuit current Continuous to VSOUT / 2 ±45 mA
TA = –40°C to +125°C ±20 ±60
FREQUENCY RESPONSE
BW Bandwidth, –3dB G < 10 6.5 MHz
G = 10, 20 5.0
G = 50, 100 2.5
SR Slew rate G = 0.5, VOUT = 8V
G = 1 to 20, VOUT = 10V		 43 V/µs
tS Settling time G = 0.5, VIN = 10V step or
G= 1 to 20, VOUT = 10V step		 To 0.01% 0.71 µs
To 0.0015% 0.88 µs
G = 50
VOUT = 10V step		 To 0.01% 1.21 µs
To 0.0015% 1.40 µs
G = 100
VOUT = 10V step		 To 0.01% 2.01 µs
To 0.0015% 2.20 µs
Gain switching time 1.5 µs
THD+N Total harmonic distortion and Noise Differential input, f = 10kHz, VOUT = 10VPP –97 dB
Single-ended input, f = 10kHz, VOUT = 10VPP –99
HD2 Second-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –132
Single-ended input, f = 10kHz, VOUT = 10VPP –112
HD3 Third-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –106
Single-ended input, f = 10kHz, VOUT = 10VPP –106
REFERENCE INPUT
Reference input voltage VLVSS VLVDD V
Reference input impedance 10 kΩ
Reference input current VIN = 0V 140 µA
Reference gain to output 1 V/V
Reference gain error VOUT = ±10V, within the linear operating range 0.01 0.05 %
INPUT STAGE POWER SUPPLY
IQ_input Input stage quiescent current
VS+, VS–		 VIN = 0V, VICM = 0V 3.2 3.9 mA
TA = –40°C to +125°C 4.9
OUTPUT STAGE POWER SUPPLY
IQ_output Output stage quiescent current
LVDD, LVSS		 VIN = 0V, VREF = 0V 1.3 1.8 mA
TA = –40°C to +125°C 2.2
DIGITAL LOGIC
VIL Digital input logic low A0, A1, A2 pins, referred to DGND VDGND VDGND + 0.8 V
VIH Digital input logic high A0, A1, A2 pins, referred to DGND VDGND + 1.8 VS+ V
Digital input pin current A0, A1, A2 pins 1.5 3 µA
VDGND DGND voltage VS– (VS+) – 4 V
DGND reference current 4 10 µA
(1) Differential Input voltage of the PGA848 amplifier (VIN = VIN+ – VIN-). The valid input range depends on input common-mode voltage VICM, gain G, and reference voltage VREF. See Section 8.1.1
(2) Output voltage VOUT = G × VIN + VREF if VIN, VICM, and VREF are in valid linear operating range. See Section 8.1.1