SBOSAN4A August   2025  – December 2025 PGA848

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Using the Output Difference Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Linear Operating Input Range
      2. 8.1.2 Current Consumption with Differential Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 Driving a Single-Ended Input SAR ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.1 Linear Operating Input Range

The linear operating input voltage range of the PGA848 input circuitry extends within 3V (maximum) of either power supply. The device maintains excellent common-mode rejection throughout this range at all temperatures. The linear operating input common-mode range is a function of the input common-mode voltage, input differential voltage, gain, and reference input voltage.

The valid common-mode range to enable valid output voltage at no load condition are shown in Figure 8-4 to Figure 8-3.

PGA848 Input Common-Mode Voltage vs Output Voltage
VS = VSOUT = ±15V VS = ±15V, VSOUT = ±5V
VREF = 0V G = 0.5V/V
Figure 8-1 Input Common-Mode Voltage vs Output Voltage
PGA848 Input Common-Mode Voltage vs Output Voltage
VS = VSOUT = ±15V VS = VSOUT = ±5V
VREF = 0V G = 2V/V
Figure 8-3 Input Common-Mode Voltage vs Output Voltage
PGA848 Input Common-Mode Voltage vs Output Voltage
VS = VSOUT = ±15V VS = VSOUT = ±5V
VREF = 0V G = 1V/V
Figure 8-2 Input Common-Mode Voltage vs Output Voltage
PGA848 Input Common-Mode Voltage vs Output Voltage
VS = VSOUT = ±15V VS = VSOUT = ±5V
VREF = 0V G = 100V/V
Figure 8-4 Input Common-Mode Voltage vs Output Voltage