SCAS414AE
November 1992 – August 2025
SN74LVC244A
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Operating Characteristics
5.8
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS 3-State Outputs
7.3.2
Standard CMOS Inputs
7.3.3
Clamp Diode Structure
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Operates from 1.65V to 3.6V
Inputs accept voltages to 5.5V
Specified from –40°C to +85°C and
–40°C to +125°C
Maximum t
pd
of 5.9ns at 3.3V
Typical V
OLP
(output ground bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
Typical V
OHV
(output V
OH
undershoot)
> 2V at V
CC
= 3.3V, T
A
= 25°C
Supports mixed-mode signal operation on
all ports (5V input or output voltage with
3.3V V
CC
)
I
off
supports live insertion, partial-power-down mode, and back-drive protection
Can be used as a down translator to translate inputs from a maximum of 5.5V down
to the V
CC
level
Available in ultra small logic QFN package (0.5mm maximum height)
Latch-up performance exceeds 250mA per
JESD 17