SCAS414AE November   1992  – August 2025 SN74LVC244A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Features

  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Specified from –40°C to +85°C and
    –40°C to +125°C
  • Maximum tpd of 5.9ns at 3.3V
  • Typical VOLP (output ground bounce)
    < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    > 2V at VCC = 3.3V, TA = 25°C
  • Supports mixed-mode signal operation on
    all ports (5V input or output voltage with
    3.3V VCC)
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Can be used as a down translator to translate inputs from a maximum of 5.5V down
    to the VCC level
  • Available in ultra small logic QFN package (0.5mm maximum height)
  • Latch-up performance exceeds 250mA per
    JESD 17