SCDA017B September 2019 – August 2026 BQ24392 , HD3SS212 , HD3SS213 , HD3SS214 , HD3SS215 , HD3SS3202 , HD3SS3212 , HD3SS3220 , HD3SS3411 , HD3SS460 , TMUXHS4212 , TS3DV642 , TS3USB221 , TS3USB221A , TS3USB221E , TS3USB30 , TS3USB3000 , TS3USB3031 , TS3USB30E , TS3USB31 , TS3USB31E , TS3USB3200 , TS5USBA224 , TS5USBC400 , TS5USBC402 , TS5USBC41 , TUSB1042I , TUSB542
PCIe (Peripheral Component Interconnect Express) is a high-speed communication protocol used to interface between a system processor and other components such as GPUs, SSDs and SmartNICs. The PCIe protocol divides its signal lanes into differential pairs for transmitting and receiving data. A single PCIe lane consists of four wires split into two pairs, ±TX (transmit pair) and ±RX (receive pair). For PCIe signaling, an ideal mux is a 1:2 or 2:1 configuration with a high rated bandwidth for better signal performance.
The mux portfolio has devices designed to support up to PCIe Gen 5 with the recent development of the TMUXHS5212.
| Part | Function | Ron (Ω) | BW (Mhz) | Supply (V) | OVP (V) | ESD | System |
|---|---|---|---|---|---|---|---|
HD3SS3212 | SPDT | 5 | 8000 | 2.7–3.6 | x | HBM 2 kv | PCIe Gen 2/3 |
HD3SS3412 | SPDT | 5 | 8000 | 3-3.6 | x | HBM 4 kv | PCIe Gen 2/3 |
TMUXHS4212 | SPDT | 5 | 13000 | 1.71–3.6 | x | HBM 2 kv | PCIe Gen 4 |
TMUXHS4412 | SPDT | 5 | 13000 | 1.71–3.6 | x | HBM 2 kv | PCIe Gen 4 |
TMUXHS5212 | SPDT | 5 | 18000 | 1.65–1.95 | x | HBM 1 kv | PCIe Gen 5 |