SCES222R April   1999  – August 2026 SN74LVC1G86

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, CL = 15pF
    7. 5.7 Switching Characteristics, CL = 30pF or 50pF
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diodes
      4. 7.3.4 Partial Power Down (Ioff)
      5. 7.3.5 Over-voltage Tolerant Inputs
    4. 7.4 Function Table
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

10 Revision History

Changes from June 1, 2017 to August 12, 2026 (from Revision Q (June 2017) to Revision R (August 2026))

  • Added Thermal Information tableGo
  • Changed Junction-to-ambient thermal resistance value for DBV package from: 206°C/W to: 357.1°C/WGo
  • Changed Junction-to-ambient thermal resistance value for DCK package from: 252°C/W to: 371°C/WGo
  • Changed tpd maximum value for VCC = 2.5V ± 0.2V from: 4.5ns to: 4.9nsGo

Changes from Revision P (September 2015) to Revision Q (June 2017)

  • Changed YZP (DSBGA) package pinout diagram and added DSBGA columnGo
  • Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down (Ioff), and Over-voltage Tolerant Inputs sectionsGo