SCHS174D February   1998  – October 2025 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3.   3
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9.   16
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 6ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Load Circuit for Push-Pull Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, Standard CMOS Inputs Pulse DurationFigure 6-2 Voltage Waveforms, Standard CMOS Inputs Pulse Duration
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, Propagation Delays for Standard CMOS Inputs
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms, Propagation Delays for Standard CMOS Inputs
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, Standard CMOS Inputs Setup and Hold TimesFigure 6-3 Voltage Waveforms, Standard CMOS Inputs Setup and Hold Times
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs
(1) The greater between tr and tf is the same as tt.
Figure 6-5 Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse DurationFigure 6-6 Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-8 Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold TimesFigure 6-7 Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times