SCHS174D February   1998  – October 2025 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3.   3
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9.   16
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

5.5 Timing Requirements

See Parameter Measurement Information
PARAMETER VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
fMAX

Maximum clock frequency

 2 6 5 4 MHz
4.5 30 25 20
6 35 29 23
tW

CLR pulse width

2 60 75 90 ns
4.5 12 15 18
6 10 13 15
tW

Clock pulse width

 2 80 100 120 ns
4.5 16 20 24
6 14 17 20
tSU

Set-up time data to clock

 2 60 75 70 ns
4.5 12 15 18
6 10 13 15
tH

Hold time, data to clock

 2 3 3 3 ns
4.5 3 3 3
6 3 3 3
tREM Removal time, CLR to clock 2 50 65 75 ns
4.5 10 13 15
6 9 11 13
HCT TYPES
fMAX

Maximum clock frequency

 4.5 25 20 16 MHz
tw

CLR pulse width

 4.5 12 15 18 ns
tw

Clock pulse width

 4.5 20 25 30 ns
tSU

Set-up time data to clock

 4.5 12 15 18 ns
tH

Hold time, data to clock

 4.5 3 3 3 ns
tREM Removal time, CLR to clock 4.5 10 13 15 ns