SCHS174D February   1998  – October 2025 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3.   3
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9.   16
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

5.4 Electrical Characteristics

PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VIH High level input voltage 2 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15
6 4.2 4.2 4.2
VIL Low level input voltage 2 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35
6 1.8 1.8 1.8
VOH

High level output voltage

CMOS loads

 IOH = – 20μA 2 1.9 1.9 1.9 V
IOH = – 20μA 4.5 4.4 4.4 4.4
IOH = – 20μA 6 5.9 5.9 5.9

High level output voltage

TTL loads

 IOH = – 4mA 4.5 3.98 3.84 3.7 V
IOH = – 5.2mA 6 5.48 5.34 5.2
VOL

Low level output voltage

CMOS loads

 IOL = 20μA 2 0.1 0.1 0.1 V
IOL = 20μA 4.5 0.1 - 0.1 - 0.1
IOL = 20μA 6 0.1 0.1 0.1

Low level output voltage

TTL loads

 IOL = 4mA 4.5 0.26 0.33 0.4 V
IOL = 5.2mA 6 0.26 0.33 0.4
II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 mA
ICC Quiescent device current VI = VCC or GND 6 8 80 160 mA
HCT TYPES
VIH High level input voltage 4.5 to 5.5 2 2 2 V
VIL Low level input voltage 4.5 to 5.5 0.8 0.8 0.8 V
VOH

High level output voltage

CMOS loads

 IOH = – 20μA 4.5 4.4 4.4 4.4 V

High level output voltage

TTL loads

 IOH = – 4mA 4.5 3.98 3.84 3.7
VOL

Low level output voltage

CMOS loads

 IOL = 20μA 4.5 0.1 0.1 0.1 V

Low level output voltage

TTL loads

 IOL = 4mA 4.5 0.26 0.33 0.4
II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA
ICC Quiescent device current VI = VCC or GND 5.5 8 80 160 μA
ΔICC(1) Additional quiescent device current per input pin CLR input held at VCC –2.1 4.5 to 5.5 100 540 675 735 μA
Data inputs held at VCC –2.1 4.5 to 5.5 100 144 180 196 μA
CLK inputs held at VCC –2.1 4.5 to 5.5 100 540 675 735 μA
(1) For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
(2) VI = VIH or VIL, unless otherwise noted.