SCHS174D February   1998  – October 2025 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3.   3
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9.   16
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

3 Description

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
CD54HC273F J (CDIP, 20) 26.92mm × 6.92mm
CD74HC273M DW (SOIC, 20) 12.80mm × 7.50mm
CD74HC273E N (PDIP, 20) 25.40mm × 6.35mm
CD74HCT273M DW (SOIC, 20) 12.80mm × 7.50mm
CD74HCT273 N (PDIP, 20) 25.40mm × 6.35mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 Functional Block DiagramFunctional Block Diagram