SCHS174D February   1998  – October 2025 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1.   1
  2. Features
  3.   3
  4. Applications
  5. Description
  6. Pin Configuration and Functions
  7. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. Parameter Measurement Information
  9.   16
  10. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

CD54HC273 CD74HC273 CD54HCT273 CD74HCT273 J, DW, or N package20-Pin CDIP, PDIP, or SOICTop View J, DW, or N package
20-Pin CDIP, PDIP, or SOIC
Top View
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
1D 3 I Input for channel 1
1Q 2 O Output for channel 1
2D 4 I Input for channel 2
2Q 5 O Output for channel 2
3D 7 I Input for channel 3
3Q 6 O Output for channel 3
4D 8 I Input for channel 4
4Q 9 O Output for channel 4
5D 13 I Input for channel 5
5Q 12 O Output for channel 5
6D 14 I Input for channel 6
6Q 15 O Output for channel 6
7D 17 I Input for channel 7
7Q 16 O Output for channel 7
8D 18 I Input for channel 8
8Q 19 O Output for channel 8
CLK 11 I Clock for all channels, rising edge triggered
CLR 1 I Clear for all channels, active low
GND 10 G Ground
VCC 20 P Positive supply
I = input, O = output, G = ground, P = power