SCHS326A January   2003  – December 2024 CD54AC109 , CD74AC109

PRODUCTION DATA  

  1.   1
  2. Features
  3. Description
  4. Pin Configuration and Functions
  5. Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Timing Requirements
    7. 4.7  Timing Requirements
    8. 4.8  Timing Requirements
    9. 4.9  Switching Characteristics
    10. 4.10 Switching Characteristics
    11. 4.11 Switching Characteristics
    12. 4.12 Operating Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Description

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE(2)
CDx4AC109 D (SOIC, 16) 9.90mm x 3.90mm
N (PDIP, 16) 19.3mm x 6.35mm
J (CDIP, 16) 19.56mm x 6.92mm
The body size (length × width) is a nominal value and does not include pins.
CD54AC109 CD74AC109 Logic
            DiagramLogic Diagram