The device incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST can be performed using various loopback modes to isolate any issues to specific parts of the data path. The BIST generates packetized data with variable content and IPG.

If generating and checking packets with the MAC is not possible, use PRBS packet generation and checking functionality to verify the data path. Perform reverse loopback with PRBS and a working link partner as follows:

1. Power and connect the PHY to a link partner.
2. Enable PRBS packet generation on the PHY (write Reg 0x0016 = 0x5000).
3. Enable reverse loopback on the link partner.
4. Wait at least one second, then check PRBS lock status on the PHY by reading register 0x16[11:10].

If register 0x16[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue can be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following procedure:

1. Write register 0x001F = 0x8000 //PHY reset
2. Write register 0x0000 = 0x2100 //Disable Auto-neg, force 100Mbps
3. Write register 0x0016 = 0x0108 //Enable Analog loopback, use 100Ω MDI terminations
4. Write register 0x0016 = 0x3108 //Enable PRBS generator and checker
5. Read register 0x0016 //Need to read 0x3B08 for PRBS active and locked
6. Read register 0x001B //Need to read 0x007D for no errors

If the internal data path is valid the issue is isolated to the MDI or the link partner.