SDAA100 April   2026 ADC12DJ5200RF , ADC32RF54 , ADC32RF55 , LMX2572 , LMX2594 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Effects of a Phase Noise Curve of a Clock on the Performance of the Converter
  6. 3 Determine Clock Performance Target Values for a Selected Data Converter
  7. 4 Narrow Down Which TI Clock to Select Based on the Specified Requirements Determined
  8. 5 Analyze the Proposed Clock's Jitter on a Converter's Performance
  9. 6 Understanding Clocking Performance Effects on the SNR of the Converter
    1. 6.1 Limitations from TI Clocking Parts When Paired with TI High-Speed Converters
  10. 7 Summary
  11. 8 References
  12. 9 Appendix A: Clock Tree Architect (CTA) Detailed Step-By-Step Guide
  13. 10Appendix B: Using PLLatinum Sim to Represent Clock Jitter for an Application's Integrated Bandwidth
  14. 11Appendix C: PLLatinum Sim Phase Noise Curves Comparison Step-by-Step Guide
  15. 12Appendix D: Comparing Phase Noise Curve Simulations of PLLatinum Sim with Measured Data

4 Narrow Down Which TI Clock to Select Based on the Specified Requirements Determined

TI's Clock Tree Architect (CTA) is a synthesis tool that proposes clock trees based on system requirements. The tool searches through an extensive database of TI top clocking products to generate system-level clock trees.

Note: CTA uses an integration bandwidth from 12kHz to 20MHz and therefore, does not consider the proposed clock's phase noise below 12kHz offsets. If a user needs to consider the close-in phase noise of the clock, see Section 10.

Fill out all inputs required by CTA and be as specific as possible. Use the jitter and noise floor calculated from Section 3 for the jitter and noise floor boxes on the Outputs section (these boxes are optional, click on the + Add requirements button to expose them). The jitter represents the integrated noise power from 12kHz to 20MHz and the noise floor represents the phase noise beyond 20MHz offset.

Apart from these two inputs, CTA allows the user to enter other characteristics about application and clocking needs. As seen on Figure 4-1, the user can input specific output requirements, input characteristics, and overall system requirements. All of this information allows CTA to give a more holistic clocking suggestion. For a more detailed CTA step-by-step how-to guide, see Section 9.

Clock Tree Architect Tool Figure 4-1 Clock Tree Architect Tool

After entering the required jitter, noise floor, and output frequency into CTA, the tool outputs either a list with valid clocking suggestions or a pop-up message stating that no design was found. In the latter case, CTA still provides a list of clocks that nearly met all requirements, offering alternative designs.

CTA can incorrectly reject suitable clocks for your application. The analog input frequency needs to be considered when the jitter of the clock is comparable to the jitter performance of the converter. For the ADC12DJ5200RF, CTA does not take the analog input frequency into account. Figure 4-2 demonstrates the inputs given to CTA and Figure 4-3 demonstrates the results from CTA when maximizing the performance of the ADC12DJ5200RF. Based on the results from CTA, there is no design that can achieve the specified application requirements. However, that is not true when considering an analog input frequency of 900MHz. Follow the steps in Section 5 to analyze how to select a clock when needing to consider the analog input frequency. For a detailed explanation of how the analog input frequency impacts the overall performance, see Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge.

Clock Tree Architect Inputs to Obtain Clock Suggestions that Maximize the Performance of the ADC12DJ5200RF at 5200MSPS Figure 4-2 Clock Tree Architect Inputs to Obtain Clock Suggestions that Maximize the Performance of the ADC12DJ5200RF at 5200MSPS
Clock Tree Architect Solutions When Maximizing the Performance of the ADC12DJ5200RF Figure 4-3 Clock Tree Architect Solutions When Maximizing the Performance of the ADC12DJ5200RF

Assume that the clock performance target values are relaxed. The clock jitter needs to be < 55fs and the noise floor < -155dBc/Hz. The list of clocking suggestions is shown in Figure 4-4

Clock Suggestions When Inputting Less Stringent Requirements Figure 4-4 Clock Suggestions When Inputting Less Stringent Requirements