SDAA281 July   2026 BQ34Z100-R2

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Minimum Parameters
    1. 2.1  Design Capacity
    2. 2.2  Design Voltage
    3. 2.3  Design Energy
    4. 2.4  Load Mode
    5. 2.5  Load Select
    6. 2.6  Cell Charging Voltage TX-TY
    7. 2.7  Number of Series Cell
    8. 2.8  Flash Update OK Cell Voltage
    9. 2.9  Cell Terminate Voltage
    10. 2.10 Taper Current
    11. 2.11 DSG Current Threshold
    12. 2.12 CHG Current Threshold
    13. 2.13 Quit Current Threshold
    14. 2.14 ChemID
  6. 3 Learning Cycle
  7. 4 Calibration
    1. 4.1 Current Calibration
    2. 4.2 Voltage Calibration and Voltage Divider
    3. 4.3 CC Offset Routine
  8. 5 Scaling
  9. 6 Additional Key Parameters and Features
    1. 6.1 OCV Wait Time
    2. 6.2 SOH Load I
    3. 6.3 Voltage Divider Parameter
    4. 6.4 RA Table Limiters
    5. 6.5 T Rise and T Time Constant
    6. 6.6 Auto Calibration
    7. 6.7 Smoothing
    8. 6.8 Sealed SRECs
  10. 7 Hardware
    1. 7.1 VEN Pin
    2. 7.2 Thermistor
    3. 7.3 Sense Resistor
    4. 7.4 Voltage Divider Calculation
    5. 7.5 LEDs
  11. 8 Chemistries
    1. 8.1 LFP
    2. 8.2 NiMH/NiCd
  12. 9 Debugging
  13. 10G1
  14. 11Reference Design
  15. 12Summary
  16. 13References

2.1 Design Capacity

Design Capacity is the capacity of the entire pack in mAh. This can be calculated by multiplying the capacity of a single cell by the number of cells in parallel for the entire pack. For example, for a 3s2p pack, where the capacity of a single cell is 1000mAh, the Design Capacity for this pack is 2000mAh, assuming there is a Curr Scale value of 1.

Design Capacity = [(capacity of a single cell) × (number of cells in parallel)]/Curr Scale