SDAA378 August   2026 ADS125H18

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Understanding ADS125H18 OWCS Operation
    2. 2.2 Using OWCS with Single-Ended Input Signals
      1. 2.2.1 Analyzing OWCS Behavior for Single-Ended Input Signals
      2. 2.2.2 Verifying OWCS Operation with a Single-Ended Input Using the ADS125H18EVM
        1. 2.2.2.1 Verifying OWCS Operation with a Single-Ended Input
        2. 2.2.2.2 Using a Fewer Number of Conversions for OWCS with a Single-Ended Input
          1. 2.2.2.2.1 Unsettled Data for Single-Ended Inputs
          2. 2.2.2.2.2 Settled Data for Single-Ended Inputs
        3. 2.2.2.3 How Input Capacitance Affects OWCS Performance for Single-Ended Inputs
        4. 2.2.2.4 Using the ADS125H18 Programmable Delay to Mitigate Settling Effects for Single-Ended Inputs
    3. 2.3 Using OWCS with Differential Input Signals
      1. 2.3.1 Analyzing OWCS Behavior for Differential Input Signals
      2. 2.3.2 Verifying OWCS Operation with a Differential Input Using the ADS125H18EVM
        1. 2.3.2.1 Verifying OWCS Operation with a Differential Input
        2. 2.3.2.2 Using a Fewer Number of Conversions for OWCS with a Differential Input
          1. 2.3.2.2.1 Unsettled Data for Differential Inputs
          2. 2.3.2.2.2 Settled Data for Differential Inputs
        3. 2.3.2.3 How Input Capacitance Affects OWCS Performance for Differential Inputs
          1. 2.3.2.3.1 Back-to-Back, Differential OWCS Measurements with Input Capacitance
        4. 2.3.2.4 Using the ADS125H18 Programmable Delay to Mitigate Settling Effects for Differential Inputs
    4. 2.4 Using the ADS125H18 Channel Sequencer to Implement an OWCS Algorithm
      1. 2.4.1 Example: Configuring the ADS125H18 Sequencer for the OWCS Algorithm
      2. 2.4.2 Understanding the OWCS Algorithm in the ADS125H18 Example Code
        1. 2.4.2.1 Initialization
          1. 2.4.2.1.1 Initialize the sequencer
          2. 2.4.2.1.2 Enter the "_step" Array Values
          3. 2.4.2.1.3 Analyze the Sequence
        2. 2.4.2.2 Starting the Sequencer and Processing Data
          1. 2.4.2.2.1 Update OWCS Step Values and Calculate "total_conversions"
          2. 2.4.2.2.2 Starting the Sequencer and Taking Data
          3. 2.4.2.2.3 Processing the OWCS Data
          4. 2.4.2.2.4 Using the OWCS Results
  6. 3Summary
  7. 4References
  8. 5Appendix A
    1. 5.1 Using OWCS with Redundant Systems
      1. 5.1.1 Dual, Redundant Systems versus Single-Device Systems
      2. 5.1.2 Using 1x OWCS versus 2x OWCS in a Dual Redundant System
      3. 5.1.3 Error Sources in Dual, Redundant Systems
        1. 5.1.3.1 RA1 and RB1 Errors
        2. 5.1.3.2 RA2 and RB2 Errors
        3. 5.1.3.3 VREF1 and VREF2 Errors
      4. 5.1.4 Measuring Differential Inputs in a Dual, Redundant System
      5. 5.1.5 Dual, Redundant System Summary

2.2.2.4 Using the ADS125H18 Programmable Delay to Mitigate Settling Effects for Single-Ended Inputs

The ADS125H18 integrates a programmable delay feature that can be used to wait for any external settling behavior to stabilize before the ADC starts converting. This delay occurs before the first conversion after a conversion START as well as at the beginning of every new sequence step when the ADC sequencer is active. The delay value can range from 0 to 65535 modulator periods, tMOD, and is independently programmable per step.

For example, Equation 9 and Equation 10 calculate one tMOD in microseconds when fMOD = 12.8MHz and the number of tMOD periods required for a 1ms delay, respectively:

Equation 9. tMOD (µs) = 1fMOD= 112.8MHz = 0.078125µs
Equation 10. tMOD (periods) = Delay (µs) tMOD (µs)= 1000µs0.078125µs= 12800

Figure 2-14 shows a logic analyzer capture of the ADS125H18 data ready (DRDY) signal in yellow. DRDY indicates when new data is ready to be clocked out of the ADC. The time between DRDY pulses measures the sample-to-sample conversion latency. The green box indicates when the ADS125H18 sequencer automatically transitions from Step 1 (OWCS disabled) and starts converting on Step 2 (OWCS enabled). The ADC uses the sinc4 filter, operates at ODR = 12.5kSPS, and has DELAY = 0 such that the first conversion latency is approximately 320µs highlighted in red. The blue box indicates that all subsequent conversions are available at 1 / ODR.

ADS125H18 DRDY Timing with Programmable Delay = 0d (Single-Ended Input, Sinc4 Filter, ODR = 12.5kSPS)Figure 2-14 ADS125H18 DRDY Timing with Programmable Delay = 0d (Single-Ended Input, Sinc4 Filter, ODR = 12.5kSPS)

Comparatively, Figure 2-15 shows the same behavior as Figure 2-14 except that DELAY = 12800 (1ms). The red highlighted box indicates that the first conversion latency is one millisecond longer as a result. The subsequent conversion latency in blue remains unchanged.

ADS125H18 DRDY Timing with Programmable Delay = 12800d (Single-Ended Input, Sinc4 Filter, ODR = 12.5kSPS)Figure 2-15 ADS125H18 DRDY Timing with Programmable Delay = 12800d (Single-Ended Input, Sinc4 Filter, ODR = 12.5kSPS)

Importantly, the delay feature only postpones the ADC sampling process such that the sequencer immediately enables the OWCS feature at "Step 2 START". This delay provides additional time for the OWCS feature to settle before the ADC conversion process begins, resulting in higher-accuracy measurements. Table 2-8 compares the measured and predicted results when RSOURCE = 800kΩ, ODR = 12.5kSPS, and input capacitance = 10nF for two DELAY values: 0ms and 1ms

Table 2-8 Measured OWCSDelta and Predicted RSOURCE_OWCS for Programmable Delay = 0ms and 1ms (Single-Ended Input, RSOURCE = 800kΩ, ODR = 12.5kSPS, Input Capacitance = 10nF)
ODRDELAY = 0msDELAY = 1ms
OWCSDelta_SERSOURCE_OWCS (kΩ)ErrorOWCSDelta_SERSOURCE_OWCS (kΩ)Error
12.5kSPS23.19%480.9140%23.34%632.3021%

Table 2-8 shows that the programmable delay helps reduce the error between the actual and predicted RSOURCE values by approximately 20%. This delay provides more stable measurements by enabling the ADC to capture less of the capacitor charging behavior and more of the steady-state behavior. Figure 2-16 shows this behavior by plotting the OWCSDelta_SE values point-by-point instead of the single value averaged over 512 conversions shown in Table 2-8. Figure 2-16 uses RSOURCE = 800kΩ, ODR = 12.5kSPS, input capacitance = 10nF, and two different DELAY values: 0ms and 1ms

OWCSDelta Behavior when Programmable Delay = 0ms and 1ms (Single-Ended Input, RSOURCE = 800kΩ, Input Capacitance = 10nF, ODR = 12.5kSPS)Figure 2-16 OWCSDelta Behavior when Programmable Delay = 0ms and 1ms (Single-Ended Input, RSOURCE = 800kΩ, Input Capacitance = 10nF, ODR = 12.5kSPS)

Figure 2-16 shows how the programmable delay avoids most of the initial capacitor charging behavior to yield an average value closer to the expected. Additional delay could improve this behavior further. Finally, Figure 2-16 shows how a specific delay time affects the OWCS performance for a specific set of ODR and input capacitance parameters. A different delay value might be required if the user changes any of these system parameters.