SDAA401 June   2026 ISOW1050 , ISOW3080 , ISOW6441 , ISOW6442 , ISOW6442-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Enhancing EMC Performance Through Board Design Techniques
    1. 2.1  HF Decoupling Capacitor on Pin 1 and Pin 16
    2. 2.2  Capacitor Bank and Relative Placement
    3. 2.3  Ferrite Bead π-Filter on Supply Rails
    4. 2.4  Isolated Copper Island (KOZ) Under Ferrite Beads
    5. 2.5  Common-Mode Choke on the CAN/RS-485 Cable (ISOW3080 and ISOW1050 Device)
    6. 2.6  Post Island Capacitor
    7. 2.7  Series Resistors or Low-Pass Filter on I/O Traces
    8. 2.8  Y-Capacitor Between GND1 and GND2 (Safety-Critical)
    9. 2.9  Interlayer Capacitor (Substrate Capacitor in the Isolation Region)
    10. 2.10 100µF Bulk Capacitor at VDD Input Rail
  6. 3Summary
  7. 4References

2.2 Capacitor Bank and Relative Placement

Proper capacitor stacking maintains low impedance across wide frequency bands:

  • 60MHz (switching fundamental): 100nF handles this
  • 1–30MHz (harmonics and common mode): 1µF provides the impedance floor
  • < 1MHz (low-frequency transients): 10µF absorbs load step current

The correct order: Smallest → Largest, Closest → Farthest from the device under test (DUT):

Refer to capacitance banks [(C27, C25, C22) and (C28, C29, C30)] placement in Figure 2-1. The order is crucial because each mm of PCB trace between capacitor and IC adds ≅1nH of series inductance. By placing large 10µF capacitors closest to the IC and small 100nF capacitors farthest from the IC, this inverts the impedance profile and results in poor HF noise shunting. For applications targeting lower supply ripple, increasing the bulk capacitor from the standard 10µF to 22µF or 47µF helps to improve supply ripple.