SDAA401 June   2026 ISOW1050 , ISOW3080 , ISOW6441 , ISOW6442 , ISOW6442-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Enhancing EMC Performance Through Board Design Techniques
    1. 2.1  HF Decoupling Capacitor on Pin 1 and Pin 16
    2. 2.2  Capacitor Bank and Relative Placement
    3. 2.3  Ferrite Bead π-Filter on Supply Rails
    4. 2.4  Isolated Copper Island (KOZ) Under Ferrite Beads
    5. 2.5  Common-Mode Choke on the CAN/RS-485 Cable (ISOW3080 and ISOW1050 Device)
    6. 2.6  Post Island Capacitor
    7. 2.7  Series Resistors or Low-Pass Filter on I/O Traces
    8. 2.8  Y-Capacitor Between GND1 and GND2 (Safety-Critical)
    9. 2.9  Interlayer Capacitor (Substrate Capacitor in the Isolation Region)
    10. 2.10 100µF Bulk Capacitor at VDD Input Rail
  6. 3Summary
  7. 4References

2.9 Interlayer Capacitor (Substrate Capacitor in the Isolation Region)

Using Y-capacitors on the printed circuit board (PCB) introduces lead inductance on both sides of the capacitor, in addition to the parasitic inductance of the capacitor, making the capacitor ineffective at frequencies higher than 200MHz. One way to create a low-inductance capacitance is by overlapping the internal PCB layers. This can be possible by a multilayer PCB layout. Extending the internal reference layers (GND and VCC) on either side of the isolation barrier (as shown in Figure 2-3) creates an overlap of internal layers. This overlap area, formed by the extension of the GND1 and VCC2 layers with FR4 material between the layers acting as a dielectric, creates a stitching capacitance between GND1 and VCC2.

Depending on whether the isolation requirement is functional, basic, or reinforced and depending on the working voltage, the spacing between the layers can be adjusted to achieve the capacitance value. Refer to the Low-Emission Designs With ISOW7841 Integrated Signal application report for an interlayer capacitance design example.

ISOW6441 ISOW3080 ISOW1050 Diagram Showing Interlayer Capacitance Using PCB Layers Figure 2-3 Diagram Showing Interlayer Capacitance Using PCB Layers

Extra care must be given at the edges of the PCB. At the edges, the planes can be exposed to air. Since opposite voltages come close to the edge of the board, these opposing voltages can potentially lead to electric field stress and then air breakdown along the edge.