SDAA403 June   2026 TIC12400-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Polling Mode Operation
    1. 2.1 Polling Cycle Architecture
    2. 2.2 Polling Timing Parameters
    3. 2.3 Register Update Behavior During a Polling Cycle
    4. 2.4 Device Startup Sequence and First Polling Cycle
  6. 3/INT Pin Leakage Current and Interrupt Handling
    1. 3.1 /INT Pin Leakage Specification
    2. 3.2 Interrupt Generation and Configuration
    3. 3.3 Startup Interrupt Behavior and Wakeup Signal Timing
  7. 4Summary
  8. 5References
Application Note

Understanding Polling Mode Operation and Interrupt Behavior of the TIC12400-Q1