SDAA403 June   2026 TIC12400-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Polling Mode Operation
    1. 2.1 Polling Cycle Architecture
    2. 2.2 Polling Timing Parameters
    3. 2.3 Register Update Behavior During a Polling Cycle
    4. 2.4 Device Startup Sequence and First Polling Cycle
  6. 3/INT Pin Leakage Current and Interrupt Handling
    1. 3.1 /INT Pin Leakage Specification
    2. 3.2 Interrupt Generation and Configuration
    3. 3.3 Startup Interrupt Behavior and Wakeup Signal Timing
  7. 4Summary
  8. 5References

2.3 Register Update Behavior During a Polling Cycle

The ADC_STATx registers hold the most recently sampled value for each INx channel. Understanding when these registers are updated is important for SPI read timing.

The following clarifications apply:

  • Per-channel update: Each INx channel's ADC_STATx register is updated immediately after that channel is sampled within the current polling cycle — not at the end of the full cycle. Channels sampled earlier in the sequence will have current-cycle values while channels not yet sampled still hold the previous-cycle value.
  • Atomic register reads: A SPI read always returns the complete, most recently stored register value. It is not possible to read a partially updated register. If a read occurs in the middle of a polling cycle, the host will receive a mix of current-cycle and previous-cycle values across different channels, depending on which channels have been sampled at the time of the read.
  • Register retention (R vs. RC types): Register bits with access type "R" retain their value after a SPI read. Register bits with access type "RC" (Read-Clear) are reset to their default value immediately after the read. Refer to the TIC12400-Q1 datasheet register map for the specific type of each bit.

NOTE: If the application requires all channels to reflect the same polling cycle, the SPI read should be timed to occur after the INT assertion that marks the end of a complete polling cycle, and before the start of the next cycle's sampling phase.